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81.发明申请CHEMICAL-MECHANICAL PLANARIZATION PROCESS USING SILICON OXYNITRIDE ANTIREFLECTIVE LAYER 有权使用硅氧烷抗反射层的化学机械平面化方法公开(公告)号：US20170069507A1
公开(公告)日：2017-03-09
申请号：US15120323
申请日：2015-04-30
发明人： Qiang HUA , Yaohui ZHOU
IPC分类号： H01L21/3105 , H01L21/02
CPC分类号： H01L21/31056 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/3081 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/76 , H01L21/762
摘要： A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the silicon nitride layer (S330).
摘要翻译： 使用氮氧化硅防反射层（S340）的化学机械抛光工艺包括：（S1）提供包括基板的半导体晶片（S310），形成在基板上的氧化层（S320）（S310），氮化硅 形成在氧化层上的层（S330）（S320），形成在氮化硅层上的防反射层（S340）（S330），延伸穿过防反射层（S340）并进入衬底（S310）的沟槽， 和填充该沟槽并覆盖防反射层的第一二氧化硅层（S350）（S340）; （S2）抛光第一二氧化硅层（S350），直到防反射层（S340）曝光; （S3）通过干蚀刻去除抗反射层（S340）; （S4）在去除了防反射层（S340）的半导体晶片的表面上形成第二二氧化硅层（S360） （S5）研磨第二二氧化硅层（S360），直到氮化硅层（S330）露出为止; （S6），除去氮化硅层（S330）。
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公开(公告)号：US09379538B2
公开(公告)日：2016-06-28
申请号：US14357724
申请日：2012-11-09
发明人： Guoding Dai , Xiaohui Ma , ChaoYao Xue , Jian Ou , Jing Lu
摘要： An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage protection function.
摘要翻译： 一种用于功率因数校正的输出过压保护电路，包括芯片外部补偿网络，芯片外部电阻分压网络，静态过电压检测电路，动态过电压检测电路和比较电路; 芯片外部补偿网络连接在芯片外部电阻分压网络和动态过压检测电路之间，芯片外部补偿网络将动态过电压信号转换转换为动态电流信号，并将其传送到动态过电压 检测电路，动态过电压检测电路检测动态电流信号，最终产生动态过电压信号（DYOVP）; 动态过电压信号（DYOVP）被输入到比较电路中，其将动态过电压信号（DYOVP）转换为与参考电压相比的电压，并输出过压控制信号（OVP），以便 实现动态过压保护功能。
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公开(公告)号：US20150354945A1
公开(公告)日：2015-12-10
申请号：US14762837
申请日：2013-12-31
发明人： Wei Huang
CPC分类号： G03F7/70625 , G01B11/02 , H01L22/12 , H01L23/544
摘要： A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.
摘要翻译： 提供了划线槽的带宽的测试结构，该结构包括彼此垂直的第一隔离线（232）和第二隔离线（234），测试结构还包括第一场区域图案 220），第一场区域图案（220）包括两个图形，两个图形各自位于第一隔离线（232）的一侧并且彼此相对。 还公开了划线槽的带宽的测试方法。 模拟LOCOS结构的场氧化物区域的图形被提供在隔离线的两侧，人造地生成步骤，通过光刻形成的小尺寸源区域上的多晶硅栅极图形可以通过在线测试带宽或 在线显示和检查条带宽度，因此可以知道模具的实际情况，可以立即发现由基板的反射引起的多晶硅栅极的宽度和形态异常。
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84.发明授权公开(公告)号：US09190897B2
公开(公告)日：2015-11-17
申请号：US14358566
申请日：2012-11-09
发明人： Guoding Dai , Yue Chen , Xiaohui Ma , Hui Han , Renyue Ma
IPC分类号： G05F3/02 , H02M1/42 , H03K17/687 , H03K17/16 , H03K17/0412 , H03K17/615 , H02M1/08 , H02M1/12 , H02M1/38 , H02M1/44
CPC分类号： H02M1/4208 , H02M1/08 , H02M1/12 , H02M1/38 , H02M1/42 , H02M1/44 , H03K17/0412 , H03K17/162 , H03K17/615 , H03K17/687 , H03K17/6877 , H03K2217/0081 , Y02B70/12 , Y02P80/112
摘要： A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a Darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range. Adding dead time control into the level shift circuit not only prevents the momentary heavy-current from a power supply to the ground during the level conversion process, but also reduces the static power consumption of the drive circuit.
摘要翻译： 一种应用于功率因数校正器的高压大电流驱动电路，包括电流镜电路（1），电平移位电路（3），高电压预调制电路（2），死区时间控制电路 （4）和大电流输出级（5）; 大电流输出级采用达林顿输出级结构，以增加驱动电路的最大工作频率。 使用稳压二极管的稳定的击穿电压特性来确保驱动电路在安全电压范围内工作。 在电平转换电路中加入死区时间控制不仅可以防止在电平转换过程中瞬间的大电流来自地电源，而且可以降低驱动电路的静态功耗。
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公开(公告)号：US20240304720A1
公开(公告)日：2024-09-12
申请号：US18576942
申请日：2022-12-14
发明人： Huajun JIN , Liang SONG , Yongshun LI , Mei YUAN , Yanan WANG , Lin LUO , Qiang ZHANG
CPC分类号： H01L29/7816 , H01L29/0603 , H01L29/66681
摘要： The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.
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公开(公告)号：US20240290846A1
公开(公告)日：2024-08-29
申请号：US18572595
申请日：2022-04-28
发明人： Qun LIU , Song ZHANG , Yaohui ZHOU , Dejin WANG , Wenming ZHU
CPC分类号： H01L29/401 , H01L29/456
摘要： A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.
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公开(公告)号：US20240234520A9
公开(公告)日：2024-07-11
申请号：US18277658
申请日：2021-07-28
发明人： CHUNXU LI , FENG LIN , SHUXIAN CHEN , HONGFENG JIN , HUAJUN JIN , GANG HUANG , YU HUANG , BIN YANG
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/401 , H01L29/66681 , H01L29/7816
摘要： A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.
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公开(公告)号：US12022270B2
公开(公告)日：2024-06-25
申请号：US17761669
申请日：2020-05-26
发明人： Jiale Su , Guoping Zhou , Xinwei Zhang , Changfeng Xia
CPC分类号： H04R31/003 , B81C1/00158 , H04R19/04 , B81C2201/0105 , B81C2201/0116 , B81C2201/0133 , H04R2201/003
摘要： A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.
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公开(公告)号：US11887979B2
公开(公告)日：2024-01-30
申请号：US17267835
申请日：2019-08-15
发明人： Shikang Cheng , Yan Gu , Sen Zhang
IPC分类号： H01L27/02 , H01L29/66 , H01L29/866
CPC分类号： H01L27/0255 , H01L27/0262 , H01L27/0296 , H01L29/66106 , H01L29/866
摘要： A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.
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公开(公告)号：US20240006492A1
公开(公告)日：2024-01-04
申请号：US18258180
申请日：2021-08-10
IPC分类号： H01L29/10 , H01L29/417 , H01L29/78 , H01L21/265 , H01L29/66
CPC分类号： H01L29/1095 , H01L29/41741 , H01L29/7813 , H01L21/26513 , H01L29/66727 , H01L29/66734
摘要： The present disclosure relates to a semiconductor device and a manufacturing method therefor. The semiconductor device includes: a base, where a first surface of the base is provided with a first trench and a second trench; a gate, provided in the first trench; a gate insulation isolation structure, provided in the first trench, wherein the gate insulation isolation structure covers the gate at a bottom, sides and a top of the gate; a source doped region, provided in the base, on both sides of the first trench and on both sides of the second trench; a trench conductive structure, provided in the second trench; a source electrode, provided on the trench conductive structure and the source doped region, and electrically connected to the trench conductive structure and the source doped region; and a drain electrode, provided on a second surface of the base. The semiconductor device in the present disclosure, in addition to be conducted through a channel, can also be conducted through the trench conductive structure; thus, conductivity thereof is stronger. Since the channel conducts faster, a turn-on voltage (forward voltage drop) thereof is lower.
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