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    Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
    81.
    发明授权
    Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer 有权
    用于形成（111）取向的含铝导体层的电离金属等离子体（IMP）方法

    公开(公告)号：US06207568B1

    公开(公告)日：2001-03-27

    申请号：US09200554

    申请日：1998-11-27

    Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC: H01L2144

    CPC classification number: H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

    Abstract translation: 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

    Self aligned dual damascene process and structure with low parasitic capacitance
    82.
    发明授权
    Self aligned dual damascene process and structure with low parasitic capacitance 有权
    自对准双镶嵌工艺和结构具有低寄生电容

    公开(公告)号：US6133144A

    公开(公告)日：2000-10-17

    申请号：US368864

    申请日：1999-08-06

    Applicant: Ming-Hsing Tsai ,  Shau-Lin Shue

    Inventor： Ming-Hsing Tsai ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/4763

    CPC classification number: H01L21/7681

    Abstract: An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures. This process reduces processing time, reduces the cost of ownership, (compatible with low dielectric constant materials) and at the same time produces a product with superior lines and via contact structures (by use of special etch stop or etch barrier layer patterning), hence improving reliability.

    Abstract translation: 已经开发了用于制造独特的互连导线和通孔接触结构的改进和新颖的工艺。 使用这种特殊的自对准双镶嵌工艺，形成了具有低寄生电容（低RC时间常数）的特殊互连导线和通孔触点。 本发明包括使用双蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是蚀刻停止或蚀刻阻挡层的特殊图案化。 这是本发明优于现有技术方法的优点，其需要具有对二氧化硅，SiO 2（增加寄生电容）的蚀刻选择性的连续的厚的停止层。 然而，在本发明中，提出了一种易于处理并具有低寄生电容的自对准双镶嵌工艺和结构。 重复自对准双镶嵌加工步骤，构建多层导电结构。 这个过程减少了处理时间，降低了所有权成本（与低介电常数材料兼容），同时产生了具有优异线条和通孔接触结构的产品（通过使用特殊的蚀刻阻挡层或蚀刻阻挡层图案），因此 提高可靠性。

    Method for forming a multi-anchor DRAM capacitor and capacitor formed
    83.
    发明授权
    Method for forming a multi-anchor DRAM capacitor and capacitor formed 失效
    形成多锚式DRAM电容器和电容器的方法

    公开(公告)号：US6015735A

    公开(公告)日：2000-01-18

    申请号：US6509

    申请日：1998-01-13

    Applicant: Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

    Inventor： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/302

    CPC classification number: H01L27/1085 ,  H01L28/86

    Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

    Abstract translation: 本发明公开了一种用于形成DRAM电容器的方法，该DRAM电容器通过利用首先沉积掺杂和未掺杂电介质材料的交替层的沉积工艺具有改善的电荷存储容量，然后将深UV型光致抗蚀剂层沉积在氧化物层的顶部 使得在用于电池开口的高密度等离子体蚀刻工艺期间，当在蚀刻室中暴露于UV发射时，光致抗蚀剂层产生酸性反应产物，使得电池开口的侧壁以不均匀的方式横向蚀刻，即， 掺杂的介电层比非掺杂的介电层更严格地被蚀刻，从而形成额外的表面积和改善的形成的电容器的电荷存储容量。

    COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME
    86.
    发明申请
    COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    铜相互连接结构及其形成方法

    公开(公告)号：US20130270702A1

    公开(公告)日：2013-10-17

    申请号：US13586676

    申请日：2012-08-15

    Applicant: Chen-Hua YU ,  Shau-Lin SHUE ,  Hsiang-Huan LEE ,  Ching-Fu YEH

    Inventor： Chen-Hua YU ,  Shau-Lin SHUE ,  Hsiang-Huan LEE ,  Ching-Fu YEH

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

    Abstract: A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

    Abstract translation: 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

    Transitional interface between metal and dielectric in interconnect structures
    88.
    发明授权
    Transitional interface between metal and dielectric in interconnect structures 有权
    互连结构中金属和电介质之间的过渡界面

    公开(公告)号：US08349730B2

    公开(公告)日：2013-01-08

    申请号：US12823649

    申请日：2010-06-25

    Applicant: Chien-Hsueh Shih ,  Shau-Lin Shue

    Inventor： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC: H01L21/44 ,  H01L23/52

    CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    Abstract translation: 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。

    Apparatus for electrochemical plating semiconductor wafers
    89.
    发明授权
    Apparatus for electrochemical plating semiconductor wafers 有权
    电化学电镀半导体晶片的装置

    公开(公告)号：US08277619B2

    公开(公告)日：2012-10-02

    申请号：US13176839

    申请日：2011-07-06

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25B9/04 ,  C25B9/02 ,  C25D17/04 ,  C25D17/06

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: An electroplating apparatus for depositing a conductive material on a semiconductor wafer includes a vessel for holding an electroplating bath, a support for holding a semiconductor wafer within the vessel and beneath a surface of the bath; first and second electrodes within the vessel, between which an electrical current may flow causing conductive material to be electrolytically deposited onto the wafer, a third electrode disposed outside of the bath for applying a static electric charge to the wafer, and an electrical power supply coupled with the third electrode.

    Abstract translation: 用于在半导体晶片上沉积导电材料的电镀设备包括用于保持电镀槽的容器，用于将半导体晶片保持在容器内并在浴表面下方的支撑体; 容器内的第一和第二电极，电流可以在其间流动，导致导电材料被电解沉积到晶片上;第三电极，设置在电镀槽的外面，用于向晶片施加静电荷;以及电源， 与第三电极。

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