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81.发明授权公开(公告)号：US07778099B2
公开(公告)日：2010-08-17
申请号：US12258970
申请日：2008-10-27
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.
摘要翻译： 提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元 请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出 延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。
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公开(公告)号：US07730232B2
公开(公告)日：2010-06-01
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。
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83.发明申请公开(公告)号：US20090161468A1
公开(公告)日：2009-06-25
申请号：US12258970
申请日：2008-10-27
申请人： Shinya FUJIOKA
发明人： Shinya FUJIOKA
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.
摘要翻译： 提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元 请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出 延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。
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84.发明授权公开(公告)号：US07200059B2
公开(公告)日：2007-04-03
申请号：US11260486
申请日：2005-10-28
IPC分类号： G11C29/00
CPC分类号： G11C29/06 , G11C29/10 , G11C2029/0405 , G11C2029/1204 , G11C2029/3602
摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.
摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。
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公开(公告)号：US20070014178A1
公开(公告)日：2007-01-18
申请号：US11515853
申请日：2006-09-06
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
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公开(公告)号：US20050259492A1
公开(公告)日：2005-11-24
申请号：US11024737
申请日：2004-12-30
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C11/4193 , G11C7/10 , G11C7/22 , G11C11/406 , G11C11/407 , G11C11/4195 , G11C11/4197 , G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。
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公开(公告)号：US06947347B2
公开(公告)日：2005-09-20
申请号：US10623544
申请日：2003-07-22
申请人： Shinya Fujioka
发明人： Shinya Fujioka
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
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公开(公告)号：US20050094480A1
公开(公告)日：2005-05-05
申请号：US11001619
申请日：2004-12-02
申请人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
发明人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/4193 , G11C8/02
CPC分类号： G11C7/1018 , G11C7/22 , G11C2207/2227
摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。
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公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译： 形成多个第一存储块和用于再现第一存储块的数据的第二存储块。 当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。 当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。 因此，可以在不被用户识别的情况下进行刷新操作。 即，可以提供用户友好的半导体存储器。
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公开(公告)号：US06643809B2
公开(公告)日：2003-11-04
申请号：US09764415
申请日：2001-01-19
申请人： Hiroyoshi Tsuboi , Shinya Fujioka
发明人： Hiroyoshi Tsuboi , Shinya Fujioka
IPC分类号： G01R328
CPC分类号： G11C29/46 , G01R31/31701
摘要： A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.
摘要翻译： 具有用于测试半导体器件的测试模式的半导体器件被提供有一个电路，该电路基于输入到其中的虚拟命令信号产生第一信号，并产生指示进入相应测试的第二信号 模式或基于地址信号和第一信号从对应的测试模式退出。
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