公开(公告)号：US06429101B1

公开(公告)日：2002-08-06

申请号：US09240753

申请日：1999-01-29

申请人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

发明人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

IPC分类号： H01L2120

CPC分类号： H01L21/02126 ,  H01L21/0214 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/31662

摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

摘要翻译： 一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。 在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

公开(公告)号：US06399458B1

公开(公告)日：2002-06-04

申请号：US09400676

申请日：1999-09-21

申请人： Douglas D. Coolbaugh ,  David L. Harame

发明人： Douglas D. Coolbaugh ,  David L. Harame

IPC分类号： H01L2120

CPC分类号： H01L21/26513 ,  H01L21/02381 ,  H01L21/02667 ,  H01L21/2022

摘要： A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

公开(公告)号：US08338265B2

公开(公告)日：2012-12-25

申请号：US12269069

申请日：2008-11-12

申请人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

发明人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC分类号： H01L21/76

CPC分类号： H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US08030167B2

公开(公告)日：2011-10-04

申请号：US11839106

申请日：2007-08-15

申请人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

IPC分类号： H01L21/33 ,  H01L27/102 ,  H01L29/73

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US08022496B2

公开(公告)日：2011-09-20

申请号：US11873696

申请日：2007-10-17

申请人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

IPC分类号： H01L29/47

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

公开(公告)号：US07714412B2

公开(公告)日：2010-05-11

申请号：US10711144

申请日：2004-08-27

申请人： Douglas D. Coolbaugh ,  Douglas B. Hershberger ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Douglas B. Hershberger ,  Robert M. Rassel

IPC分类号： H01L29/93

CPC分类号： H01L29/93 ,  H01L29/94

摘要： The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.

摘要翻译： 本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于 所述第二导电类型。 接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。 在一些情况下，在本发明方法的这一点形成掺杂区域。 阱区包括第二导电类型的外阱区和第一导电类型的内阱区。 所述阱区的每个阱在上表面被隔离区分开。 然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。

公开(公告)号：US07112535B2

公开(公告)日：2006-09-26

申请号：US10605439

申请日：2003-09-30

申请人： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

IPC分类号： H01L21/302

CPC分类号： H01L27/0738 ,  H01L27/0802 ,  H01L28/20

摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

摘要翻译： 公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。 该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后是在多晶硅上沉积保护性介电层的步骤，将掺杂剂通过保护电介质层注入到多晶硅中 限定多晶硅电阻器的电阻，并形成硅化物。

公开(公告)号：US06958506B2

公开(公告)日：2005-10-25

申请号：US10688508

申请日：2003-10-17

申请人： Evgeni P. Gousev ,  Harald F. Okorn-Schmidt ,  Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh

发明人： Evgeni P. Gousev ,  Harald F. Okorn-Schmidt ,  Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh

IPC分类号： H01L29/73 ,  H01L21/02 ,  H01L21/28 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/51 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

摘要翻译： 提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器 结构体。 本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。 本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

公开(公告)号：US06667207B2

公开(公告)日：2003-12-23

申请号：US10246110

申请日：2002-09-18

申请人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

发明人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

IPC分类号： H01L218249

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

摘要翻译： 提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器 结构体。 本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。 本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

公开(公告)号：US06656815B2

公开(公告)日：2003-12-02

申请号：US09826054

申请日：2001-04-04

申请人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

IPC分类号： H01L2176

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.