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273 条记录 (耗时 0.031 秒)

    Pattern density control using edge printing processes
    82.
    发明授权
    Pattern density control using edge printing processes 有权
    图案密度控制采用边缘印刷工艺

    公开(公告)号：US07358140B2

    公开(公告)日：2008-04-15

    申请号：US11163968

    申请日：2005-11-04

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L27/1052 ,  Y10S438/95

    摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.

    摘要翻译： 一种结构制造方法。 该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。 接下来，提供实际结构，其包括（i）与设计基板对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层 层。 接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

    Sidewall image transfer (SIT) technologies
    86.
    发明授权
    Sidewall image transfer (SIT) technologies 失效
    侧墙图像传输（SIT）技术

    公开(公告)号：US07265013B2

    公开(公告)日：2007-09-04

    申请号：US11162662

    申请日：2005-09-19

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

    IPC分类号： H01L21/8242 ,  H01L21/336

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132

    摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.

    摘要翻译： 一种结构制造方法。 该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。 然后，定位区域缩进。 然后，在结构的暴露于环境的表面上形成保形层。 然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。 然后，去除封盖区域，以将定位区域暴露于周围环境。 然后，移除定位区域，以将存储区域暴露于周围环境。 然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

    Vertical dual gate field effect transistor
    87.
    发明授权
    Vertical dual gate field effect transistor 失效
    垂直双栅场效应晶体管

    公开(公告)号：US07176089B2

    公开(公告)日：2007-02-13

    申请号：US10853177

    申请日：2004-05-26

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

    摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    摘要翻译： 一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

    Method of independent P and N gate length control of FET device made by sidewall image transfer technique
    88.
    发明授权
    Method of independent P and N gate length control of FET device made by sidewall image transfer technique 失效
    由侧壁图像传输技术制造的FET器件的独立P和N栅极长度控制方法

    公开(公告)号：US06998332B2

    公开(公告)日：2006-02-14

    申请号：US10754073

    申请日：2004-01-08

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/2815

    摘要： Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.

    摘要翻译： 公开了一种在基板上形成导电层并在导电层上方形成牺牲结构的方法。 接下来，本发明使用能够经历尺寸变化的间隔物材料形成邻近牺牲结构的侧壁间隔，此后本发明在将侧壁间隔物留在适当位置的情况下去除牺牲结构。 然后，本发明使用牺牲掩模保护所选择的侧壁间隔物，并且使侧壁间隔物中的其它侧壁隔离件不被保护。 这允许本发明选择性地将未受保护的侧壁间隔物暴露于改变未受保护的侧壁间隔物的尺寸的处理。 这导致未受保护的侧壁间隔件具有与受保护的侧壁间隔物不同的尺寸。 然后，本发明移除牺牲掩模，并且使用侧壁间隔物作为栅极导体掩模来图案化导电层，以在衬底上产生不同尺寸的栅极导体。 接下来，本发明移除侧壁间隔物并形成与栅极导体相邻的源极，漏极和沟道区域。