公开(公告)号：US5627391A

公开(公告)日：1997-05-06

申请号：US492913

申请日：1995-06-20

申请人： Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

发明人： Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L29/76 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L27/11502 ,  H01L28/40

摘要： A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at the bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.

摘要翻译： 半导体器件包括其上形成有集成电路的硅衬底1，形成在硅衬底1上的第一绝缘层6，包括形成在第一绝缘层6上的下电极7的电容器，具有高介电常数的电介质膜8和上电极9 具有接触孔13的第二绝缘膜11，其独立地引导到下电极7和上电极9，在接触孔13的底部接触下电极7和上电极9的扩散阻挡层17和扩散形成的互连层15 在接触孔13的底部的扩散阻挡层17中形成由粒状晶体构成的层状区域。

公开(公告)号：US5012651A

公开(公告)日：1991-05-07

申请号：US457234

申请日：1989-12-26

申请人： Kazuo Nakatani ,  Mitsuhiro Ikoma ,  Yuji Yoshida ,  Takeshi Tomizawa ,  Koji Arita ,  Minoru Tagashira

发明人： Kazuo Nakatani ,  Mitsuhiro Ikoma ,  Yuji Yoshida ,  Takeshi Tomizawa ,  Koji Arita ,  Minoru Tagashira

IPC分类号： F25B9/00 ,  F25B13/00

CPC分类号： F25B13/00 ,  F25B9/006

摘要： The structure is arranged in such a manner that nonazeotropic mixed refrigerant is enclosed therein and a fractioning/separating device is disposed in a low pressure circuit in the main circuit of refrigerating cycle so as to conduct separation operation, the fraction/separation can be conducted at a low pressure in a separation mode, the specific volume of refrigerant gas generated in a reservoir due to heat supplied from a heater is enlarged, and the velocity of gas which moves upwards in the fractioning/separating device can be increased, causing a gas-liquid contact to be promoted. As a result, high performance separation can be conducted at reduced quantity of heat, causing the density of high boiling point refrigerant reserved to be significantly raised. Thus, the composition in the main circuit becomes a composition enriched with low boiling point refrigerant exhibiting excellent heating performance so as to satisfactorily cope with an increase in the load.

公开(公告)号：US08482958B2

公开(公告)日：2013-07-09

申请号：US13321018

申请日：2011-03-10

申请人： Yukio Hayakawa ,  Koji Arita ,  Takumi Mikawa ,  Takeki Ninomiya

发明人： Yukio Hayakawa ,  Koji Arita ,  Takumi Mikawa ,  Takeki Ninomiya

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  H01L45/146

摘要： Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0

摘要翻译： 提供了即使当施加具有不同极性的电脉冲并且可能导致大电流流过可变电阻元件时也能够防止写入干扰的电流导向元件。 当前的转向元件包括第一电极（32），第二电极（31）和电流转向层（33）。 当前的转向层（33）包括加入氢或氟的SiNx（其中0 <0.85）。 当D（D = D0×1022原子/ cm3）表示氢或氟的密度时，d（nm）表示电流导向层（33）的厚度，V0（V）表示适用于第一 电极（32）和第二电极（31）D，x，d和V0满足下式。 （ln（1000（C·exp（α·d）exp（β·x））-1）γ）2 @ V0 ）γ）2-（ln（10000（C·exp（α·d）exp（β·x））-1）γ）2/2> = 0其中C = k1×D0k2，α，β， k1和k2是常数。

公开(公告)号：US08355274B2

公开(公告)日：2013-01-15

申请号：US13061312

申请日：2009-09-17

申请人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru IIjima ,  Kenji Tominaga

发明人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru IIjima ,  Kenji Tominaga

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0

摘要翻译： 即使施加具有不同极性的电脉冲也能够防止写入干扰的发生，并且可能导致大的电流流过可变电阻元件并且可以无限制地写入数据的电流导向元件。 在一种存储元件（3）中，包括：可变电阻元件（1），其电阻值响应于具有正极性和负极性的电脉冲的应用而变化并且保持改变的电阻值; 以及当施加电脉冲时转向流过可变电阻元件（1）的电流的当前操舵元件（2），所述电流操舵元件（2）包括：第一电极（32）; 第二电极（31）; 和介于所述第一电极（32）和所述第二电极（31）之间的电流转向层（33）。 当电流导向层（33）包括SiNx（0

公开(公告)号：US08295123B2

公开(公告)日：2012-10-23

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： G11C13/00

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US20120256156A1

公开(公告)日：2012-10-11

申请号：US13515592

申请日：2010-11-17

申请人： Koji Arita ,  Takumi Mikawa

发明人： Koji Arita ,  Takumi Mikawa

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： G11C13/0007 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： Disclosed is a memory device provided with a plurality of memory cells and a lead-out line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed above a substrate (1) and a variable resistance element (10) having a lower electrode (7), an upper electrode (9) that comprises a noble metal, and a variable resistance layer (8) disposed between the lower electrode (7) and the upper electrode (9). The resistance value of the variable resistance layer (8) changes reversibly in response to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The lead-out line (12) is in direct contact with the upper electrodes (9) of the memory cells.

摘要翻译： 公开了一种设置有多个存储单元和在存储单元之间共享的引出线（12）的存储器件。 每个存储单元设置有形成在基板（1）上方的晶体管（6）和具有下电极（7）的可变电阻元件（10），包含贵金属的上电极（9）和可变电阻 层（8）设置在下电极（7）和上电极（9）之间。 可变电阻层（8）的电阻值响应于通过晶体管（6）的电脉冲而可逆地改变并施加在下电极（7）和上电极（9）之间。 引出线（12）与存储单元的上电极（9）直接接触。

公开(公告)号：US08038864B2

公开(公告)日：2011-10-18

申请号：US11829129

申请日：2007-07-27

申请人： Koji Arita ,  Ryohei Kitao

发明人： Koji Arita ,  Ryohei Kitao

IPC分类号： C25D21/12

CPC分类号： C25D21/12 ,  H01L21/2885 ,  H01L21/76877

摘要： A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr=S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.

摘要翻译： 制造本发明的半导体器件的方法包括：用导电材料填充设置在形成在基板上的绝缘膜的多个凹槽的电镀工艺，其中所述电镀工艺包括执行步骤（S104）的工艺步骤（S104） 以第一电流密度进行电镀，该第一电流密度通过基于第一表面积S1的表面积Sr = S1 / S2在衬底的整个表面上的比率校正预定的第一参考电流密度而得到，该第一电流密度包括 在半导体基板的整个表面上的多个凹部和在不包括多个凹部的侧壁的区域的基板的整个表面上的第二表面区域S2，当不大于预定宽度的细凹槽时， 在所有多个凹部中，填充有导电材料。

公开(公告)号：US07981760B2

公开(公告)日：2011-07-19

申请号：US12669812

申请日：2009-05-07

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

摘要翻译： 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

公开(公告)号：US07960770B2

公开(公告)日：2011-06-14

申请号：US12445380

申请日：2007-10-12

申请人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

发明人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC分类号： H01L29/76

CPC分类号： H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

摘要翻译： 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US20110002155A1

公开(公告)日：2011-01-06

申请号：US12677413

申请日：2009-05-01

申请人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： G11C11/00 ,  H01L29/47 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/24 ,  H01L45/00

摘要： A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises α-tungsten.

摘要翻译： 一种存储元件（3），其以矩阵形式布置在存储器件中，并且包括响应于施加到其上的正或负电脉冲而切换其电阻值的电阻可变元件（1），并保持所述开关电阻值; 以及电流控制元件（2），用于控制当电脉冲施加到电阻可变元件（1）时流动的电流; 其中所述电流控制元件（2）包括第一电极; 第二电极; 以及夹在所述第一电极和所述第二电极之间的电流控制层; 并且其中所述电流控制层包括SiN x，并且所述第一电极和所述第二电极中的至少一个包括α-钨。