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公开(公告)号:US07215024B2
公开(公告)日:2007-05-08
申请号:US10936922
申请日:2004-09-08
IPC分类号: H01L23/48
CPC分类号: H01L21/76843 , H01L21/32051 , H01L21/32136 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.
摘要翻译: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构,沉积薄金属阻挡层。 金属阻挡层被氧化,然后沉积两层,第一层包含掺杂的铜,第二层包含纯铜。 双镶嵌结构填充铜,进行热退火,稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。
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82.
公开(公告)号:US07030023B2
公开(公告)日:2006-04-18
申请号:US10655972
申请日:2003-09-04
申请人: Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
发明人: Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
IPC分类号: H01L21/302
CPC分类号: H01L21/3105 , H01L21/28556 , H01L21/76807 , H01L21/76814 , H01L21/76838 , H01L21/76843 , H01L21/76873
摘要: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.
摘要翻译: 一种用于形成铜镶嵌特征的方法,包括提供半导体工艺晶片,其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口,以及覆盖所述至少一个通孔开口的上覆沟槽开口,以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片,进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。
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公开(公告)号:US06943111B2
公开(公告)日:2005-09-13
申请号:US10361732
申请日:2003-02-10
申请人: Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
发明人: Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
IPC分类号: H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/44
CPC分类号: H01L21/76843 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.
摘要翻译: 提供了一种用于创建铜种子界面能力的新方法。 在介电层中的开口上方设置有铜合金的第一籽晶层和铜的第二晶种层。 开口填充有铜,第一和第二种子层被退火。
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84.
公开(公告)号:US20050189075A1
公开(公告)日:2005-09-01
申请号:US10789660
申请日:2004-02-27
申请人: Shing-Chyang Pan , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Ching-Hua Hsieh , Chao-Hsien Peng , Li-Lin Su , Shau-Lin Shue
发明人: Shing-Chyang Pan , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Ching-Hua Hsieh , Chao-Hsien Peng , Li-Lin Su , Shau-Lin Shue
CPC分类号: H01L21/67109 , B08B7/0071 , H01J37/32862
摘要: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.
摘要翻译: 一种反应性预清洁室,其包含诸如高温静电卡盘(HTESC)的晶片加热装置,用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁(RPC)工艺所需的最佳温度。 此外,脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。
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公开(公告)号:US20140035135A1
公开(公告)日:2014-02-06
申请号:US13572302
申请日:2012-08-10
申请人: Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
CPC分类号: H01L24/13 , H01L23/49816 , H01L24/11 , H01L2224/118 , H01L2224/13 , H01L2224/13016 , H01L2224/131 , H01L2224/1319 , H01L2924/01029 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/15788 , H01L2924/37001 , H01L2924/00
摘要: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
摘要翻译: 用于球栅阵列(BGA)的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属(UBM)层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度,并且凸块高度比凸块宽度的比值小于1。
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公开(公告)号:US08536573B2
公开(公告)日:2013-09-17
申请号:US13310448
申请日:2011-12-02
申请人: Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
CPC分类号: H01L22/32 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05027 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05684 , H01L2224/05686 , H01L2224/11464 , H01L2224/11825 , H01L2224/13006 , H01L2224/13082 , H01L2224/13083 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01079 , H01L2924/04941 , H01L2224/05552
摘要: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.
摘要翻译: 提供了一种用于电镀连接到测试垫的触点的系统和方法。 一个实施例包括将阻塞材料插入到接触件和测试垫之间的通孔中。 在另一个实施例中,阻挡结构可以插入在接触件和测试垫之间。 在另一个实施例中,阻挡层可以插入到触点叠层中。 一旦已经形成了阻挡材料,阻挡结构或阻挡层,则可以用阻挡材料,阻挡结构或阻挡层电镀接触,从而降低或防止由于电偶效应导致的测试焊盘的劣化。
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公开(公告)号:US20130140563A1
公开(公告)日:2013-06-06
申请号:US13310448
申请日:2011-12-02
申请人: Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号: H01L23/522
CPC分类号: H01L22/32 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05027 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05684 , H01L2224/05686 , H01L2224/11464 , H01L2224/11825 , H01L2224/13006 , H01L2224/13082 , H01L2224/13083 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01079 , H01L2924/04941 , H01L2224/05552
摘要: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.
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公开(公告)号:US08034709B2
公开(公告)日:2011-10-11
申请号:US12287516
申请日:2008-10-10
申请人: Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
发明人: Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
IPC分类号: H01L21/4763
CPC分类号: H01L21/76844 , H01L21/76846 , H01L21/76862 , Y10S438/927
摘要: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.
摘要翻译: 提供了一种形成复合阻挡层的方法,该复合阻挡层具有优异的阻挡性能,并且当复合阻挡层贯穿整个半导体器件时,两种介电材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中,并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成,并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界,并且结晶层通常与诸如互连材料的导电材料形成边界。
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公开(公告)号:US20050263902A1
公开(公告)日:2005-12-01
申请号:US11174189
申请日:2005-07-01
申请人: Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
发明人: Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
IPC分类号: H01L21/768 , H01L29/40 , H01L21/44 , H01L23/48 , H01L23/52
CPC分类号: H01L21/76843 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.
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公开(公告)号:US20050029665A1
公开(公告)日:2005-02-10
申请号:US10936922
申请日:2004-09-08
IPC分类号: H01L21/31 , H01L21/3205 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号: H01L21/76843 , H01L21/32051 , H01L21/32136 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.
摘要翻译: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构,沉积薄金属阻挡层。 金属阻挡层被氧化,然后沉积两层,第一层包含掺杂的铜,第二层包含纯铜。 双镶嵌结构填充铜,进行热退火,稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。
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