公开(公告)号：US07602065B2

公开(公告)日：2009-10-13

申请号：US12042573

申请日：2008-03-05

申请人： Shang-Yun Hou ,  Chun-Hung Chen ,  Chia-Lun Tsai ,  Pao-Kang Niu ,  Shin-Puu Jeng

发明人： Shang-Yun Hou ,  Chun-Hung Chen ,  Chia-Lun Tsai ,  Pao-Kang Niu ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.

摘要翻译： 半导体器件包括第一电路，第一密封环和至少一个第一凹口。 第一密封环围绕第一回路。 第一个切口切割第一个密封圈。 具体而言，第一凹口包括内部开口，外部开口和连接凹槽。 内部开口位于第一密封环的内侧。 外部开口位于第一密封环的外侧。 外部开口和内部开口未对齐。 连接槽连接内部开口和外部开口。

公开(公告)号：US20080283969A1

公开(公告)日：2008-11-20

申请号：US11842821

申请日：2007-08-21

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/00

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

摘要翻译： 集成电路结构包括包括多个电介质层的半导体芯片，其中所述多个电介质层包括顶部电介质层; 以及与所述半导体芯片的边缘相邻的第一密封环。 集成电路结构还包括在顶部介电层上的第一钝化层; 以及从所述第一钝化层的顶表面延伸到所述第一钝化层中的沟槽，其中所述沟槽基本上形成环。 环的每一侧与半导体芯片的相应边缘相邻。 所述多个通孔中的至少一个具有大于所述多个金属线中相应的上覆金属线的宽度的约70％的宽度。

公开(公告)号：US07397106B2

公开(公告)日：2008-07-08

申请号：US11299999

申请日：2005-12-12

申请人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

发明人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

IPC分类号： H01L23/62

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

摘要翻译： 提供了具有有效的热路径的半导体结构及其形成方法。 半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。 激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。 保护环通过触点热耦合到半导体衬底。 半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

公开(公告)号：US20080073753A1

公开(公告)日：2008-03-27

申请号：US11525575

申请日：2006-09-22

申请人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

摘要翻译： 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。

公开(公告)号：US20080020559A1

公开(公告)日：2008-01-24

申请号：US11458501

申请日：2006-07-19

申请人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01L21/44

CPC分类号： H01L21/76895 ,  H01L22/34 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/30105

摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

摘要翻译： 互连结构至少包括第一互连层和第二互连层。 第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。 第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。 第一和第二互连层的焊盘结构彼此连接。

公开(公告)号：US20130273694A1

公开(公告)日：2013-10-17

申请号：US13444662

申请日：2012-04-11

申请人： Cheng-Chieh Hsieh ,  Shang-Yun Hou ,  Shin-Pun Jeng

发明人： Cheng-Chieh Hsieh ,  Shang-Yun Hou ,  Shin-Pun Jeng

IPC分类号： H01L21/822

CPC分类号： H01L21/50 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33107 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00

摘要： A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.

摘要翻译： 一种方法包括通过粘合剂将晶片附着在载体上，并在载体中形成沟槽以将载体转换成散热器。 散热器，载体和粘合剂被锯成多个包装。

公开(公告)号：US20120267753A1

公开(公告)日：2012-10-25

申请号：US13090606

申请日：2011-04-20

申请人： Der-Chyang Yeh ,  Shang-Yun Hou

发明人： Der-Chyang Yeh ,  Shang-Yun Hou

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.

摘要翻译： 提供一种集成电路器件及其制造方法。 集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。 所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料 和空隙区域。

公开(公告)号：US08575717B2

公开(公告)日：2013-11-05

申请号：US13090606

申请日：2011-04-20

申请人： Der-Chyang Yeh ,  Shang-Yun Hou

发明人： Der-Chyang Yeh ,  Shang-Yun Hou

IPC分类号： H01L29/86

CPC分类号： H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.

摘要翻译： 提供一种集成电路器件及其制造方法。 集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。 所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料 和空隙区域。

公开(公告)号：US20130113070A1

公开(公告)日：2013-05-09

申请号：US13292792

申请日：2011-11-09

申请人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Chun-Yi Liu ,  Hsien-Pin Hu ,  Shang-Yun Hou

发明人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Chun-Yi Liu ,  Hsien-Pin Hu ,  Shang-Yun Hou

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/525 ,  H01L23/5256 ,  H01L23/5382 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00 ,  H01L2224/81805

摘要： Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.

摘要翻译： 公开了半导体器件用插入件及其制造方法。 在一个实施例中，插入器包括衬底，设置在衬底上的接触焊盘以及耦合到接触焊盘的衬底中的第一通孔。 第一保险丝耦合到第一通孔。 衬底中的第二通孔耦合到接触焊盘，并且第二保险丝耦合到第二通孔。

公开(公告)号：US07888236B2

公开(公告)日：2011-02-15

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。