-
81.发明申请Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers 有权生长III-V化合物半导体从填充中间层的沟槽公开(公告)号：US20110117730A1
公开(公告)日：2011-05-19
申请号：US12842221
申请日：2010-07-23
IPC分类号： H01L21/20
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/02463 , H01L21/0254 , H01L21/02546 , H01L21/02617 , H01L21/02639
摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
摘要翻译： 形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。 多个半导体柱由绝缘层的一部分水平隔开。 以周期性图案分配多个半导体柱。 该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。
-
82.发明申请公开(公告)号：US20110086491A1
公开(公告)日：2011-04-14
申请号：US12842546
申请日：2010-07-23
IPC分类号： H01L21/762
CPC分类号： H01L21/02546 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02639 , H01L21/76224 , H01L29/045 , H01L29/0665 , H01L29/66522
摘要： A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.
摘要翻译： 形成集成电路结构的方法包括提供具有硅衬底的晶片; 在硅衬底中形成多个浅沟槽隔离（STI）区域; 以及通过去除多个STI区域的相对侧壁之间的硅衬底的顶部来形成凹陷。 硅衬底中的所有凹部的基本上所有的长边在相同的方向上延伸。 然后在凹部中外延生长III-V族化合物半导体材料。
-
83.发明申请High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio 有权具有改进的接通电流比的高移动性多栅极晶体管公开(公告)号：US20100252816A1
公开(公告)日：2010-10-07
申请号：US12639653
申请日：2009-12-16
CPC分类号： H01L29/8124 , H01L29/1054 , H01L29/122 , H01L29/66431 , H01L29/66484 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/812
摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.
摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。
-
84.发明申请A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device 有权用于应变硅MOSFET器件的嵌入式多晶硅栅极结构公开(公告)号：US20060009001A1
公开(公告)日：2006-01-12
申请号：US10864952
申请日：2004-06-10
申请人： Yi-Chun Huang , Bor-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Huan-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
发明人： Yi-Chun Huang , Bor-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Huan-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76
CPC分类号： H01L29/66545 , H01L21/823807 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
摘要翻译： 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。
-
公开(公告)号：US09246004B2
公开(公告)日：2016-01-26
申请号：US13296723
申请日：2011-11-15
IPC分类号： H01L29/78 , H01L21/3065 , H01L29/08 , H01L29/267 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/0653 , H01L29/0847 , H01L29/20 , H01L29/22 , H01L29/267 , H01L29/66628 , H01L29/66636 , H01L29/66795
摘要： A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film adjoining the sidewall of the STI.
摘要翻译： 公开了半导体器件的应变结构。 半导体器件的示例性结构包括：包括主表面的衬底; 在基板的主表面上的栅极堆叠; 设置在所述栅极堆叠的一侧上的浅沟槽隔离（STI），其中所述STI位于所述衬底内; 以及填充有分布在所述栅叠层和所述STI之间的应变结构的空腔，其中所述空腔包括由所述STI形成的一个侧壁，由所述基板形成的一个侧壁和由所述基板形成的底表面，其中所述应变结构包括 SiGe层和邻接STI侧壁的第一应变膜。
-
公开(公告)号：US09184050B2
公开(公告)日：2015-11-10
申请号：US12847877
申请日：2010-07-30
IPC分类号： H01L21/20 , H01L21/02 , H01L21/762 , H01L29/04 , H01L29/06
CPC分类号： H01L21/76283 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/31111 , H01L21/32055 , H01L21/76224 , H01L21/76272 , H01L29/045 , H01L29/0657 , H01L29/0692 , H01L29/2003
摘要： A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.
摘要翻译： 提供具有外延层的半导体器件的制造方法。 半导体器件具有形成在其中的沟槽的衬底和形成在沟槽下方的凹部。 凹槽具有（111）晶体取向的侧壁。 沟槽的深度使得深度大于或等于凹部的侧壁长度的二分之一。 在凹槽和沟槽中形成外延层。 沟槽的深度足以引起在半导体衬底和外延层的界面之间形成的位错，从而沿沟槽的侧壁终止。
-
公开(公告)号：US09105654B2
公开(公告)日：2015-08-11
申请号：US13426106
申请日：2012-03-21
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.
摘要翻译： 一个实施例是FinFET器件。 FinFET器件包括鳍片，第一源极/漏极区域，第二源极/漏极区域和沟道区域。 翅片升高到基底之上。 第一源/漏区和第二源极/漏极区在鳍中。 沟道区域横向在第一和第二源极/漏极区域之间。 沟道区域具有不平行且不垂直于衬底顶表面的刻面。
-
公开(公告)号：US08962400B2
公开(公告)日：2015-02-24
申请号：US13178294
申请日：2011-07-07
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/36 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66795 , Y10S438/933
摘要： A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
摘要翻译： 一种方法包括在半导体区域上形成栅极叠层，并使半导体区域凹陷以形成邻近栅叠层的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源。 在外延生长含硅半导体区域的步骤期间，砷原位被掺杂。
-
89.发明授权High-mobility multiple-gate transistor with improved on-to-off current ratio 有权具有改善的导通截止电流比的高迁移率多栅极晶体管公开(公告)号：US08674341B2
公开(公告)日：2014-03-18
申请号：US12639653
申请日：2009-12-16
IPC分类号： H01L21/336
CPC分类号： H01L29/8124 , H01L29/1054 , H01L29/122 , H01L29/66431 , H01L29/66484 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/812
摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.
摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。
-
公开(公告)号：US08618556B2
公开(公告)日：2013-12-31
申请号：US13174170
申请日：2011-06-30
CPC分类号： H01L21/823821 , H01L27/0924 , H01L29/1054 , H01L29/785
摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.
摘要翻译： 公开了一种集成电路器件及其制造方法。 示例性器件包括具有衬底表面的半导体衬底和设置在半导体衬底中的用于隔离器件的NMOS区域和器件的PMOS区域的沟槽隔离结构。 该器件还包括第一鳍结构，其包括设置在具有高带隙能量和晶格常数大于Ge的III-V半导体材料的层上的硅或SiGe; 包括硅或SiGe的第二鳍结构，其设置在具有高带隙能量和比Ge小的晶格常数的III-V半导体材料层上; 以及设置在垂直于第一和第二鳍结构并且布置在其上的栅极结构。
-
-
-
-
-
-
-
-
-
搜索结果
148 条记录 (耗时 0.035 秒)
