公开(公告)号：US20070224365A1

公开(公告)日：2007-09-27

申请号：US11387323

申请日：2006-03-22

申请人： Alessandro C. Callegari ,  James P. Doyle ,  Alfred Grill ,  Hideo Kimura ,  Minhua Lu ,  Vishnubhai V. Patel ,  James Vichiconti ,  Takeshi Yamada

发明人： Alessandro C. Callegari ,  James P. Doyle ,  Alfred Grill ,  Hideo Kimura ,  Minhua Lu ,  Vishnubhai V. Patel ,  James Vichiconti ,  Takeshi Yamada

IPC分类号： C09K19/00 ,  C23C16/26 ,  C08J7/18

CPC分类号： C23C16/26 ,  C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  G02F1/13378 ,  G02F2001/133746 ,  Y10T428/10

摘要： A method for providing an alignment surface for liquid crystal molecules in a liquid crystal display, comprising depositing on an optically transparent substrate an optically transparent film; and irradiating the film with nitrogen ions sufficiently to produce a pretilt angle of preferably greater than ten degrees. The film is preferably comprised of diamond like carbon. A liquid crystal display formed in accordance with the method.

摘要翻译： 一种用于在液晶显示器中提供液晶分子的取向表面的方法，包括在光学透明基底上沉积光学透明的膜; 并充分地用氮离子照射薄膜以产生优选大于十度的预倾角。 该膜优选由类金刚石碳组成。 一种根据该方法形成的液晶显示器。

公开(公告)号：US20070196639A1

公开(公告)日：2007-08-23

申请号：US11190360

申请日：2005-07-27

申请人： Stephen Gates ,  Alfred Grill ,  Deborah Neumayer ,  Son Nguyen ,  Vishnubhai Patel

发明人： Stephen Gates ,  Alfred Grill ,  Deborah Neumayer ,  Son Nguyen ,  Vishnubhai Patel

IPC分类号： B32B3/00

CPC分类号： H01B19/04 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/249967 ,  Y10T428/24997 ,  Y10T428/249978 ,  Y10T428/249979 ,  H01L2924/00

摘要： The present invention provides a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD. The inventive composite material is also characterized by the substantial absence of the broad distribution of larger sized pores which is prevalent in prior art porous composite materials. The porous composite material includes a first solid phase having a first characteristic dimension and a second solid phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.

摘要翻译： 本发明提供一种多孔复合材料，其中复合材料中的基本上所有的孔都具有小直径约5nm或更小并具有窄PSD的孔。 本发明的复合材料的特征还在于现有技术的多孔复合材料中普遍存在的较大尺寸的孔的基本上不存在。 多孔复合材料包括具有第一特征尺寸的第一固相和由具有第二特征尺寸的孔组成的第二固相，其中至少一个所述相的特征尺寸被控制为约5nm或更小的值 。

公开(公告)号：US07252875B2

公开(公告)日：2007-08-07

申请号：US10320111

申请日：2002-12-16

申请人： Stephan A. Cohen ,  Stephen McConnell Gates ,  Alfred Grill ,  Vishnubhai V. Patel

发明人： Stephan A. Cohen ,  Stephen McConnell Gates ,  Alfred Grill ,  Vishnubhai V. Patel

IPC分类号： B32B9/00

CPC分类号： H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12535 ,  Y10T428/24917 ,  Y10T428/249953 ,  H01L2924/00

摘要： A diffusion barrier useful in semiconductor electronic devices, such as multi-level interconnect wiring structures, is provided. The diffusion barrier is characterized as having a low-dielectric constant of less than 3.5, preferably less than 3.0, as well as being capable of substantially preventing Cu and/or oxygen from diffusing into the active device areas of the electronic device. Since the diffusion barrier has a low-dielectric constant, the diffusion barrier has only a minor effect on the effective dielectric constant of the interconnect structure. The low-k diffusion barrier includes atoms of Si, C, H and N. The N atoms are non-uniformly distributed within the low-k diffusion barrier. Optionally, the low-k diffusion barrier may include atoms of Ge, O, halogens such as F or any combination thereof.

摘要翻译： 提供了可用于诸如多层互连布线结构的半导体电子器件中的扩散屏障。 扩散阻挡层的特征在于具有小于3.5，优选小于3.0的低介电常数，并且能够基本上防止Cu和/或氧扩散到电子器件的有源器件区域。 由于扩散阻挡层具有低介电常数，所以扩散阻挡层对互连结构的有效介电常数只有较小的影响。 低k扩散势垒包括Si，C，H和N的原子.N原子在低k扩散势垒内不均匀分布。 任选地，低k扩散阻挡层可以包括Ge，O的原子，诸如F的卤素或其任何组合。

公开(公告)号：US20070122989A1

公开(公告)日：2007-05-31

申请号：US11618770

申请日：2006-12-30

申请人： Jack Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Meyerson ,  John Ott

发明人： Jack Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Meyerson ,  John Ott

IPC分类号： H01L29/00 ,  H01L21/331

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US07186573B2

公开(公告)日：2007-03-06

申请号：US11263024

申请日：2005-10-31

申请人： James William Adkisson ,  Charles Thomas Black ,  Alfred Grill ,  Randy William Mann ,  Deborah Ann Neumayer ,  Wilbur David Pricer ,  Katherine Lynn Saenger ,  Thomas McCarroll Shaw

发明人： James William Adkisson ,  Charles Thomas Black ,  Alfred Grill ,  Randy William Mann ,  Deborah Ann Neumayer ,  Wilbur David Pricer ,  Katherine Lynn Saenger ,  Thomas McCarroll Shaw

IPC分类号： H01L21/00

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

公开(公告)号：US20060110937A1

公开(公告)日：2006-05-25

申请号：US11324479

申请日：2006-01-03

申请人： Stephen Gates ,  Alfred Grill ,  David Medeiros ,  Deborah Newmayer ,  Son Nguyen ,  Vishnubhai Patel ,  Xinhui Wang

发明人： Stephen Gates ,  Alfred Grill ,  David Medeiros ,  Deborah Newmayer ,  Son Nguyen ,  Vishnubhai Patel ,  Xinhui Wang

IPC分类号： H01L21/31

CPC分类号： H01L21/3122 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695

摘要： A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

公开(公告)号：US20060049443A1

公开(公告)日：2006-03-09

申请号：US11263024

申请日：2005-10-31

申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

公开(公告)号：US20050194619A1

公开(公告)日：2005-09-08

申请号：US11040778

申请日：2005-01-21

申请人： Daniel Edelstein ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Robert Miller ,  Deborah Neumayer ,  Son Nguyen

发明人： Daniel Edelstein ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Robert Miller ,  Deborah Neumayer ,  Son Nguyen

IPC分类号： H01L27/148 ,  H01L31/103

CPC分类号： H01L31/103 ,  Y10T428/31663

摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C═C or a [S]n linkage, where n is a defined above.

摘要翻译： 提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k介电材料，其包括Si，C，O和H的原子，其中C原子的一部分键合为Si-CH _{3个官能团，另外一部分C原子键合为Si-R-Si，其中R是苯基， - [CH 2 N] - 其中n大于或等于1，HC-CH，C-CH 2，CC或[S] N n连接，其中n定义如上。}

公开(公告)号：US06908866B2

公开(公告)日：2005-06-21

申请号：US10775515

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： C23C16/32 ,  C30B25/02 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US20050059258A1

公开(公告)日：2005-03-17

申请号：US10662022

申请日：2003-09-12

申请人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

发明人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

摘要翻译： 半导体器件结构和制造方法包括具有顶部第一层的衬底; 位于所述第一层顶部的第二薄过渡层; 以及位于所述过渡层顶部的第三层，其中所述第二薄过渡层在所述结构的所述第一和第三层之间提供强粘合力和内聚强度。 此外，半导体器件结构和制造方法包括绝缘结构，其包括多个介电层和导电层，其中设置有各自的过渡键合层以增强不同层之间的界面强度。 此外，电子器件结构包括绝缘和导电材料层，作为后端线（“BEOL”）布线结构中的层间或层间电介质，其中不同对的介电膜之间的界面强度由 薄的中间过渡粘合层。