公开(公告)号：US20200098676A1

公开(公告)日：2020-03-26

申请号：US16140195

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/36

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die, having an active surface and an opposing backside surface, including a plurality of through silicon vias (TSVs); and an inductor including a first conductive pillar with a first end and an opposing second end, wherein the first end of the first conductive pillar is coupled to the backside surface of a first individual TSV; a second conductive pillar with a first end and an opposing second end, wherein the first end of the second conductive pillar is coupled to the backside surface of a second individual TSV, wherein the second end of the second conductive pillar is coupled to the second end of the first conductive pillar, and wherein the first and the second conductive pillars are at least partially surrounded in a magnetic material.

公开(公告)号：US20200075521A1

公开(公告)日：2020-03-05

申请号：US16117353

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Gerald S. Pasdast

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00 ,  H03M9/00

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

公开(公告)号：US10446461B2

公开(公告)日：2019-10-15

申请号：US15816681

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/433 ,  H01L23/42 ,  H01L23/467

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

公开(公告)号：US20190311980A1

公开(公告)日：2019-10-10

申请号：US15948803

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff ,  Thomas Sounart ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/14 ,  H01G4/008 ,  H05K1/16 ,  H01G4/30 ,  H01L21/48 ,  H05K1/18 ,  H01L41/047 ,  H01G4/12 ,  H01L41/187 ,  H01L41/053 ,  H01L41/29 ,  H01L41/314 ,  H01L29/16

Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.

公开(公告)号：US10368439B2

公开(公告)日：2019-07-30

申请号：US14778027

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Shawna M. Liff

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36 ,  H01L25/16 ,  H01L23/58 ,  H05K1/02

Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.

公开(公告)号：US10319896B2

公开(公告)日：2019-06-11

申请号：US15637682

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Ye Seul Nam ,  James S. Clarke ,  Jeanette M. Roberts ,  Roman Caudillo

IPC: H01L29/06 ,  H01L29/08 ,  H01L31/0256 ,  H01L39/22 ,  H01R3/00 ,  H05K1/00 ,  H05K9/00 ,  H01L39/04 ,  H01L25/16 ,  H01L23/538 ,  H01L23/66 ,  H01L23/552 ,  H01L39/02 ,  H01L39/24 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  G06N99/00 ,  G06N10/00

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

公开(公告)号：US10305019B1

公开(公告)日：2019-05-28

申请号：US14229820

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff

IPC: H01L41/09 ,  H01L41/23 ,  H01L41/047 ,  H01L41/053

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

公开(公告)号：US10256521B2

公开(公告)日：2019-04-09

申请号：US15280823

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Sasha N. Oster ,  Johanna M. Swan ,  Georgios C. Dogiamis ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Telesphor Kamgaing

IPC: H01P5/10 ,  H01P11/00 ,  H01P5/107

Abstract: The systems and methods described herein provide a traveling wave launcher system physically and communicably coupled to a semiconductor package and to a waveguide. The traveling wave launcher system includes a slot-line signal converter and a tapered slot launcher. The slot-line signal converter may be formed integral with the semiconductor package and includes a balun structure that converts the microstrip signal to a slot-line signal. The tapered slot launcher is communicably coupled to the slot-line signal converter and includes a first plate and a second plate that form a slot. The tapered slot launcher converts the slot-line signal to a traveling wave signal that is propagated to the waveguide.

公开(公告)号：US09822470B2

公开(公告)日：2017-11-21

申请号：US13714990

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

IPC: D03D1/00 ,  H01B7/04 ,  D02G3/44 ,  D04H3/00 ,  D01D5/00 ,  D01D5/34 ,  B21C37/04 ,  B21C23/08 ,  D04H1/4266 ,  D04H1/4382

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.

公开(公告)号：US09721880B2

公开(公告)日：2017-08-01

申请号：US14969940

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Sanka Ganesan ,  Shawna M. Liff ,  Yikang Deng ,  Debendra Mallik

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/10 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H05K1/18 ,  H05K1/03 ,  H05K3/34 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14135 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15321 ,  H01L2924/3511 ,  H05K1/03 ,  H05K1/18 ,  H05K1/181 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.