公开(公告)号：US10461172B2

公开(公告)日：2019-10-29

申请号：US15850585

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Hemanth Jagannathan ,  Yann Mignot ,  Stuart A. Sieg

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/40 ,  H01L21/311

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

公开(公告)号：US20190252263A1

公开(公告)日：2019-08-15

申请号：US16392064

申请日：2019-04-23

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Yann Mignot ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

公开(公告)号：US20190252262A1

公开(公告)日：2019-08-15

申请号：US16391990

申请日：2019-04-23

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Yann Mignot ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

公开(公告)号：US10361125B2

公开(公告)日：2019-07-23

申请号：US15846844

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Yann Mignot ,  Choonghyun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

公开(公告)号：US20190189519A1

公开(公告)日：2019-06-20

申请号：US15846844

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Yann Mignot ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

公开(公告)号：US10304744B1

公开(公告)日：2019-05-28

申请号：US15980427

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Ekmini Anuja De Silva ,  Fee Li Lie ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L21/033

Abstract: Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

公开(公告)号：US10020255B1

公开(公告)日：2018-07-10

申请号：US15798794

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Joe Lee ,  Yann Mignot ,  Hosadurga Shobha ,  Junli Wang ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

公开(公告)号：US09385078B1

公开(公告)日：2016-07-05

申请号：US15064688

申请日：2016-03-09

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

公开(公告)号：US12142562B2

公开(公告)日：2024-11-12

申请号：US17304466

申请日：2021-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Chanro Park ,  Hsueh-Chung Chen

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/033

Abstract: A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

公开(公告)号：US12142556B2

公开(公告)日：2024-11-12

申请号：US17448445

申请日：2021-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yann Mignot ,  Mary Claire Silvestre ,  Effendi Leobandung

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/552

Abstract: A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10−8 Ω·m and has a thickness of greater than or equal to 1 μm. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.