公开(公告)号：US08817524B2

公开(公告)日：2014-08-26

申请号：US13722314

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  SanDisk/Toshiba ,  Kabushiki Kaisha Toshiba

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  G11C7/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。 这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。 其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压为至少约8V。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20140185357A1

公开(公告)日：2014-07-03

申请号：US13728739

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/147 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1633

Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Abstract translation: 适用于存储器件应用的转向元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，操纵元件可以包括第一电极，第二电极和夹在两个电极之间的渐变电介质层。 渐变电介质层可以包括从第一电极到第二电极的不同组成。 带隙的顶部和/或底部的分级能级可以是梯度介电层组成的结果，和/或电极的功函数可以被配置为抑制断开的隧道和热离子电流 和/或最大化导通状态和转向元件断开状态下的隧道和热离子电流的比例。

公开(公告)号：US20140175604A1

公开(公告)日：2014-06-26

申请号：US13725701

申请日：2012-12-21

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L49/02

CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

公开(公告)号：US20140110764A1

公开(公告)日：2014-04-24

申请号：US13655838

申请日：2012-10-19

Applicant: INTERMOLECULAR INC.

Inventor： Sandip Niyogi ,  Sean Barstow ,  Dipankar Pramanik

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28202 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00635 ,  B01J2219/00745 ,  B82Y30/00 ,  C23C14/04 ,  C23C16/04 ,  C23C16/4412 ,  C23C16/45565 ,  H01J37/3244 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02304 ,  H01L21/28194 ,  H01L22/14 ,  H01L29/513

Abstract: Methods and apparatuses for combinatorial processing are disclosed. Methods of the present disclosure providing a substrate, the substrate comprising a plurality of site-isolated regions. Methods include forming a first capping layer on the surface of a first site-isolated region of the substrate. The methods further include forming a second capping layer on the surface of a second site-isolated region of the substrate. In some embodiments, forming the first and second capping layers include exposing the first and second site-isolated regions to a plasma induced with H2 and hydrocarbon gases. In some embodiments, methods include applying at least one subsequent process to each site-isolated region. In addition, methods include evaluating results of the films post processing.

Abstract translation: 公开了用于组合处理的方法和装置。 提供衬底的本公开的方法，所述衬底包括多个位点隔离区域。 方法包括在衬底的第一位置隔离区域的表面上形成第一覆盖层。 所述方法还包括在所述衬底的第二位置隔离区域的表面上形成第二覆盖层。 在一些实施方案中，形成第一和第二封盖层包括将第一和第二位点隔离区域暴露于由H 2和烃气体引起的等离子体。 在一些实施方案中，方法包括将至少一个后续过程应用于每个位点隔离区域。 此外，方法包括评估胶片后处理的结果。

公开(公告)号：US20140109030A1

公开(公告)日：2014-04-17

申请号：US13956220

申请日：2013-07-31

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G01R31/2848 ,  G01R31/2858 ,  G06F17/5036

Abstract: Methods are described for performing detailed Technology Computer Aided Design (TCAD) simulations of electromigration (EM) failure in a standard test structure suitable for the simulation of integrated circuit (IC) conductive interconnects. Methods are described for performing these simulation so as to extract from the results of these simulations criteria substantially underlying the EM lifetime of interconnects, thereby permitting rapid diagnosis of potential sites of EM failure early in the IC design and fabrication process, and thereby allowing more rapid development of reliable ICs robust against EM failure. Specific results for EM failure criteria in Cu interconnects are also presented.

Abstract translation: 描述了用于在适合于模拟集成电路（IC）导电互连的标准测试结构中进行电迁移（EM）故障的详细技术计算机辅助设计（TCAD）模拟的方法。 描述了用于执行这些模拟的方法，以从这些模拟标准的结果中提取基本上在互连的EM寿命内的标准，从而允许在IC设计和制造过程的早期快速诊断EM故障的潜在位置，从而允许更快速 开发针对EM故障的可靠IC。 还介绍了Cu互连中EM故障标准的具体结果。

公开(公告)号：US20140051223A1

公开(公告)日：2014-02-20

申请号：US14064787

申请日：2013-10-28

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

IPC: H01L45/00

CPC classification number: H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

公开(公告)号：US20130214238A1

公开(公告)日：2013-08-22

申请号：US13804318

申请日：2013-03-14

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

公开(公告)号：US09343673B2

公开(公告)日：2016-05-17

申请号：US14598499

申请日：2015-01-16

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00 ,  H01L27/10 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

公开(公告)号：US09337238B1

公开(公告)日：2016-05-10

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/50 ,  H01L33/32 ,  H01L33/30 ,  H01L33/28 ,  H01L33/40

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。

公开(公告)号：US20160118440A1

公开(公告)日：2016-04-28

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/40 ,  H01L33/32 ,  H01L33/50 ,  H01L33/28 ,  H01L33/30

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。