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    Ultrathin Coating for One Way Mirror Applications
    2.
    发明申请
    Ultrathin Coating for One Way Mirror Applications 审中-公开
    用于单向镜应用的超薄涂层

    公开(公告)号：US20140268377A1

    公开(公告)日：2014-09-18

    申请号：US14105118

    申请日：2013-12-12

    Applicant: Intermolecular, Inc.

    Inventor： Xuena Zhang ,  Dipankar Pramanik

    IPC: G02B5/08 ,  G02B1/10

    CPC classification number: G02B1/105 ,  G02B1/14 ,  G02B5/0858

    Abstract: Systems and methods for improving the performance of one way mirror applications are disclosed. Methods consistent with the present disclosure include introducing a glass substrate into a processing chamber. The processing chamber comprises a sputter target assembly disposed over the substrate. Next, depositing metal silicide material within a plurality of site-isolated regions on the substrate to form a metal silicide coating within each region. Notably, each metal silicide coating has a thickness between 0.001 and 0.5 microns. Finally, evaluating results of the metal silicide coating formed within the plurality of site-isolated regions.

    Abstract translation: 公开了用于改善单向镜应用的性能的系统和方法。 与本公开一致的方法包括将玻璃基板引入处理室。 处理室包括设置在衬底上的溅射靶组件。 接下来，在衬底上的多个位置隔离区域内沉积金属硅化物材料，以在每个区域内形成金属硅化物涂层。 值得注意的是，每个金属硅化物涂层的厚度为0.001至0.5微米。 最后，评估在多个位置隔离区域内形成的金属硅化物涂层的结果。

    Two Step Deposition of Molybdenum Dioxide Electrode for High Quality Dielectric Stacks
    3.
    发明申请
    Two Step Deposition of Molybdenum Dioxide Electrode for High Quality Dielectric Stacks 有权
    二级沉积二氧化钼电极用于高质量电介质堆叠

    公开(公告)号：US20140175604A1

    公开(公告)日：2014-06-26

    申请号：US13725701

    申请日：2012-12-21

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

    IPC: H01L49/02

    CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

    Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

    New Magnet Design Which Improves Erosion Profile for PVD Systems
    4.
    发明申请
    New Magnet Design Which Improves Erosion Profile for PVD Systems 审中-公开
    提高PVD系统侵蚀性能的新型磁铁设计

    公开(公告)号：US20140124359A1

    公开(公告)日：2014-05-08

    申请号：US13667856

    申请日：2012-11-02

    Applicant: INTERMOLECULAR, INC.

    Inventor： ShouQian Shao ,  Kent Riley Child ,  Danny Wang ,  Xuena Zhang

    IPC: C23C14/35

    CPC classification number: C23C14/042 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00754 ,  B01J2219/00756 ,  C23C14/351 ,  H01J37/3408 ,  H01J37/3452

    Abstract: Methods and apparatuses for performing combinatorial processing are disclosed. Methods include introducing a substrate into a processing chamber. The processing chamber includes a sputter assembly disposed over the substrate. The sputter assembly includes a rotatable n-fold, symmetric-shaped magnetron and a sputter target. The methods include depositing a first film on the surface of a first site-isolated region of the substrate. The methods further include depositing a second film on the surface of a second site-isolated region of the substrate. Furthermore, methods include evaluating results of the first and second films.

    Abstract translation: 公开了用于执行组合处理的方法和装置。 方法包括将衬底引入处理室。 处理室包括设置在基板上方的溅射组件。 溅射组件包括可旋转的n倍对称形磁控管和溅射靶。 所述方法包括在衬底的第一位置隔离区域的表面上沉积第一膜。 该方法还包括在衬底的第二位置隔离区域的表面上沉积第二膜。 此外，方法包括评估第一和第二膜的结果。

    Low-emissivity coatings
    5.
    发明授权
    Low-emissivity coatings 有权
    低辐射涂层

    公开(公告)号：US08859093B2

    公开(公告)日：2014-10-14

    申请号：US13728889

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Xuena Zhang ,  Dipankar Pramanik

    IPC: C03C17/09 ,  C03C17/30 ,  C03C17/38 ,  C03C17/00 ,  C03C17/36

    CPC classification number: C03C17/36 ,  C03C17/3636 ,  C03C17/3644 ,  Y10T428/261 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31678

    Abstract: Embodiments of the present invention include low emissivity (low-E) coatings and methods for forming the coatings. The low-E coating comprises a self-assembled monolayer (SAM) on a glass substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the glass substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the low-E coating comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n−2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as silver. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic. The coating can further comprise an antireflection coating on the metal layer.

    Abstract translation: 本发明的实施例包括低发射率（低E）涂层和形成涂层的方法。 低E涂层包括在玻璃基板上的自组装单层（SAM），其中SAM的一个表面设置成与玻璃基板接触并共价结合到玻璃基板上，单层的一个表面设置成与 共价键合到金属层。 在一些实施方案中，低E涂层包含以下结构的一个或多个单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n， m为1〜3，L为VI族元素，M为银等金属。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。 涂层还可以包括在金属层上的抗反射涂层。

    Two step deposition of molybdenum dioxide electrode for high quality dielectric stacks
    6.
    发明授权
    Two step deposition of molybdenum dioxide electrode for high quality dielectric stacks 有权
    二级沉积二氧化钼电极用于高质量电介质叠层

    公开(公告)号：US08835310B2

    公开(公告)日：2014-09-16

    申请号：US13725701

    申请日：2012-12-21

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

    IPC: H01L21/4763 ,  H01L49/02

    CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

    Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

    Fullerene-based capacitor electrode
    7.
    发明授权
    Fullerene-based capacitor electrode 有权
    富勒烯电容器电极

    公开(公告)号：US08975134B2

    公开(公告)日：2015-03-10

    申请号：US13728026

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

    IPC: H01L21/8242 ,  H01L21/20 ,  H01L29/40 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/49 ,  H01L29/94

    CPC classification number: H01L29/401 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/94

    Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

    Abstract translation: 可以使用掺杂的富勒烯类导电材料作为电极，其可以与诸如高k电介质的电介质接触。 通过将电介质与掺杂的富勒烯类电极的带隙对准，例如，电介质的导带最小值落入掺杂的富勒烯类材料的带隙之一中，可以减少通过电介质的热离子泄漏，因为 电极中的激发的电子或空穴将需要更高的热激发能量以克服通过介电层之前的带隙。

    Diffusion barriers
    8.
    发明授权
    Diffusion barriers 有权
    扩散障碍

    公开(公告)号：US08871601B2

    公开(公告)日：2014-10-28

    申请号：US13728934

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Xuena Zhang ,  Mankoo Lee ,  Dipankar Pramanik

    IPC: H01L21/331 ,  H01L21/44 ,  H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  B82Y10/00 ,  B82Y30/00

    CPC classification number: H01L23/538 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n−2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

    Abstract translation: 本发明的实施例包括扩散阻挡层，形成屏障的方法以及利用屏障的半导体器件。 扩散阻挡层包括在半导体衬底上的自组装单层（SAM），其中SAM的一个表面设置成与半导体衬底接触并且共价键合到半导体衬底，并且单层的一个表面被设置成接触并共价键合 到金属层。 在一些实施方案中，阻挡层包含一个或多个下列结构的单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n，m为1 至3，L为VI族元素，M为金属，例如铜。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。

    Low-Emissivity Coatings
    10.
    发明申请
    Low-Emissivity Coatings 有权
    低辐射涂层

    公开(公告)号：US20140186617A1

    公开(公告)日：2014-07-03

    申请号：US13728889

    申请日：2012-12-27

    Applicant: INTERMOLECULAR, INC.

    Inventor： Xuena Zhang ,  Dipankar Pramanik

    IPC: C03C17/36 ,  C03C17/00

    CPC classification number: C03C17/36 ,  C03C17/3636 ,  C03C17/3644 ,  Y10T428/261 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31678

    Abstract: Embodiments of the present invention include low emissivity (low-E) coatings and methods for forming the coatings. The low-E coating comprises a self-assembled monolayer (SAM) on a glass substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the glass substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the low-E coating comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n-2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as silver. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic. The coating can further comprise an antireflection coating on the metal layer.

    Abstract translation: 本发明的实施例包括低发射率（低E）涂层和形成涂层的方法。 低E涂层包括在玻璃基板上的自组装单层（SAM），其中SAM的一个表面设置成与玻璃基板接触并共价结合到玻璃基板上，单层的一个表面设置成与 共价键合到金属层。 在一些实施方案中，低E涂层包含以下结构的一个或多个单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n， m为1〜3，L为VI族元素，M为银等金属。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。 涂层还可以包括在金属层上的抗反射涂层。

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