公开(公告)号：US5436483A

公开(公告)日：1995-07-25

申请号：US142965

申请日：1993-10-29

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5426613A

公开(公告)日：1995-06-20

申请号：US972907

申请日：1992-11-06

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5208782A

公开(公告)日：1993-05-04

申请号：US892708

申请日：1992-05-29

申请人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

发明人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

IPC分类号： G06F11/18 ,  G06F11/20 ,  G11C11/406 ,  G11C29/00 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C29/808 ,  G11C11/406 ,  G11C29/88 ,  H01L24/06 ,  H01L27/10805 ,  G06F11/1666 ,  G06F11/183 ,  H01L2224/4826 ,  H01L27/105 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

摘要翻译： 提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。 为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。 在芯片上提供了多个宏单元存储块通用的其他外围电路。 宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。 宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。 这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

公开(公告)号：US4562555A

公开(公告)日：1985-12-31

申请号：US535232

申请日：1983-09-23

申请人： Yoshiaki Ouchi ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa

发明人： Yoshiaki Ouchi ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04

CPC分类号： G11C7/10 ,  G11C7/1033 ,  G11C8/04

摘要： An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential. When the data is written or read serially, the pin arrangement of the package of a 256K bit dynamic RAM can be substantially the same as that of the package of a 64K bit dynamic RAM. Hence, compatibility can be established between the 256K bit dynamic RAM and a 64K bit dynamic RAM.

摘要翻译： 用于动态RAM的地址多路复用类型系统包括具有多个存储单元的存储单元阵列，这些存储单元通过从地址解码器，解码器和移位寄存器输出的信号同时选择。 动态RAM还包括选择电路，其以分时方式接收通过封装的多个引脚之一施加到外部的多个地址信号，并且使得可以将数据写入或从其中的一个存储器单元读取数据 选择多个存储单元。 当移位寄存器操作时，动态RAM可以读出或写入从存储单元阵列中选择的多个存储单元的串行数据。 动态RAM也可以简单地通过将引脚连接到预定电位，来将数据串行读取或写入从存储单元阵列中选择的多个存储单元中。 当数据被串行写入或读取时，256K位动态RAM的封装的引脚排列可以与64K位动态RAM的封装基本相同。 因此，可以在256K位动态RAM和64K位动态RAM之间建立兼容性。

公开(公告)号：US08269031B2

公开(公告)日：2012-09-18

申请号：US13287530

申请日：2011-11-02

申请人： Kazuyuki Miyazawa ,  Yukimitsu Suda

发明人： Kazuyuki Miyazawa ,  Yukimitsu Suda

IPC分类号： C07F9/11

CPC分类号： A61Q19/00 ,  A61K8/553 ,  A61K2800/56 ,  C07F9/091

摘要： A phosphorylcholine group-containing compound that is a structure having a phosphorylcholine group represented by the following formula 1 and an amino group or a group derived from an amino group in an identical compound. (In the formula, m is 2 or more and 6 or less and p is 1 or 2. Each of X1, X2 and X3 is an alkyl group whose carbon number is 1 or more and 6 or less.)

摘要翻译： 作为具有下述式1所示的磷酰胆碱基的结构的含磷酰胆碱基的化合物和氨基或由相同化合物中的氨基衍生的基团。 （式中，m为2以上且6以下，p为1或2. X1，X2和X3各自为碳原子数1以上6以下的烷基。

公开(公告)号：US08155395B2

公开(公告)日：2012-04-10

申请号：US11495326

申请日：2006-07-28

申请人： Koji Kobayashi ,  Atsushi Katsumata ,  Hiroshi Nakajima ,  Kazuyuki Miyazawa ,  Koichi Ito ,  Takafumi Aoki

发明人： Koji Kobayashi ,  Atsushi Katsumata ,  Hiroshi Nakajima ,  Kazuyuki Miyazawa ,  Koichi Ito ,  Takafumi Aoki

IPC分类号： G06K9/00

CPC分类号： G06K9/0061 ,  G06K9/522

摘要： An iris authentication apparatus includes an iris area extraction unit, registration pattern generating unit, collation pattern generating unit, and collation unit. The iris area extraction unit extracts iris areas from a sensed registration eyeball image and a sensed collation eyeball image. When the iris area extraction unit extracts an iris area from the registration eyeball image, the registration pattern generating unit generates a registration iris pattern image by performing polar coordinate transformation of an image in the extracted iris area. When the iris area extraction unit extracts an iris area from the collation eyeball image, the collation pattern generating unit generates a collation iris pattern image by performing polar coordinate transformation of an image in the extracted iris area. The collation unit collates the registration iris pattern image output from the registration pattern generating unit and the collation iris pattern image output from the collation pattern generating unit on the basis of a correlation therebetween.

摘要翻译： 虹膜认证装置包括光圈区域提取单元，注册图案生成单元，对比图案生成单元和对照单元。 虹膜区域提取单元从感测到的注册眼球图像和感测的对照眼球图像中提取虹膜区域。 当虹膜区域提取单元从登记眼球图像中提取虹膜区域时，登记图案生成单元通过对提取的虹膜区域中的图像进行极坐标变换来生成登记虹膜图案图像。 当虹膜区域提取单元从排序规则眼球图像中提取虹膜区域时，核对图案生成单元通过对提取的虹膜区域中的图像进行极坐标变换来生成排序规则虹膜图案图像。 对照单元根据它们之间的相关性对照从注册图案生成单元输出的登记虹膜图案图像和从核对图案生成单元输出的对照光圈图案图像。

公开(公告)号：US20100285252A1

公开(公告)日：2010-11-11

申请号：US12490531

申请日：2009-06-24

申请人： Kazuyuki Miyazawa ,  Taketoshi Kanda ,  Yousuke Toujo ,  Aya Ohkubo ,  Osamu Shirota ,  Kenichi Sakuma ,  Masayoshi Wada

发明人： Kazuyuki Miyazawa ,  Taketoshi Kanda ,  Yousuke Toujo ,  Aya Ohkubo ,  Osamu Shirota ,  Kenichi Sakuma ,  Masayoshi Wada

IPC分类号： B01D39/20 ,  B05D3/00 ,  B32B1/00 ,  B32B1/08

CPC分类号： B01J20/28019 ,  B01J20/103 ,  B01J20/28057 ,  B01J20/28078 ,  B01J20/286 ,  B01J20/3204 ,  B01J20/3219 ,  B01J20/3242 ,  B01J20/3259 ,  B01J20/3272 ,  B01J20/3276 ,  B01J2220/54 ,  B01J2220/58 ,  C08J7/12 ,  Y10T428/139 ,  Y10T428/2991

摘要： A method for surface modification of a material by means of introducing the phosphorylcholine group represented by the following formula (1-1) onto the surface of the material by treating a material having amino groups with a chemical compound containing an aldehyde derivative obtained by the oxidative ring-opening reaction of glycerophosphorylcholine. The method of the present invention provides various materials such as medical materials having superior biocompatibility and hydrophilicity.

摘要翻译： 通过将具有氨基的材料与含有通过氧化性的醛衍生物获得的醛衍生物的化合物进行处理，通过将下式（1-1）表示的磷酸胆碱基团引入到材料的表面上来对材料进行表面改性的方法 甘油磷酰胆碱开环反应。 本发明的方法提供了具有优异的生物相容性和亲水性的医疗材料等各种材料。

公开(公告)号：US20100221558A1

公开(公告)日：2010-09-02

申请号：US12738878

申请日：2008-10-15

申请人： Kazuyuki Miyazawa

发明人： Kazuyuki Miyazawa

IPC分类号： B05D1/36 ,  B32B9/04

CPC分类号： G01N33/54393 ,  B05D7/52 ,  C08J7/047 ,  C08J2323/12 ,  C08J2483/00 ,  G01N33/545

摘要： A surface modification method includes a step of applying, onto a material, an application fluid containing a polymer having a functional group capable of producing a silanol group through hydrolysis thereof and an alkoxysilane and a step of applying, onto the material on which the application fluid is applied, an application fluid containing a hydrophilizing agent having a functional group capable of producing a silanol group through hydrolysis thereof or a silanol group.

摘要翻译： 表面改性方法包括在材料上涂布含有能够通过其水解产生硅烷醇基的官能团的聚合物的涂布液和烷氧基硅烷的步骤，以及将涂布液施加到涂布液 使用含有能够通过其水解或硅烷醇基产生硅烷醇基的官能团的亲水剂的涂布液。

公开(公告)号：US20070025598A1

公开(公告)日：2007-02-01

申请号：US11495326

申请日：2006-07-28

申请人： Koji Kobayashi ,  Atsushi Katsumata ,  Hiroshi Nakajima ,  Kazuyuki Miyazawa ,  Koichi Ito ,  Takafumi Aoki

发明人： Koji Kobayashi ,  Atsushi Katsumata ,  Hiroshi Nakajima ,  Kazuyuki Miyazawa ,  Koichi Ito ,  Takafumi Aoki

IPC分类号： G06K9/00

CPC分类号： G06K9/0061 ,  G06K9/522

摘要： An iris authentication apparatus includes an iris area extraction unit, registration pattern generating unit, collation pattern generating unit, and collation unit. The iris area extraction unit extracts iris areas from a sensed registration eyeball image and a sensed collation eyeball image. When the iris area extraction unit extracts an iris area from the registration eyeball image, the registration pattern generating unit generates a registration iris pattern image by performing polar coordinate transformation of an image in the extracted iris area. When the iris area extraction unit extracts an iris area from the collation eyeball image, the collation pattern generating unit generates a collation iris pattern image by performing polar coordinate transformation of an image in the extracted iris area. The collation unit collates the registration iris pattern image output from the registration pattern generating unit and the collation iris pattern image output from the collation pattern generating unit on the basis of a correlation therebetween.

摘要翻译： 虹膜认证装置包括光圈区域提取单元，注册图案生成单元，对比图案生成单元和对照单元。 虹膜区域提取单元从感测到的注册眼球图像和感测的对照眼球图像中提取虹膜区域。 当虹膜区域提取单元从登记眼球图像中提取虹膜区域时，登记图案生成单元通过对提取的虹膜区域中的图像进行极坐标变换来生成登记虹膜图案图像。 当虹膜区域提取单元从排序规则眼球图像中提取虹膜区域时，核对图案生成单元通过对提取的虹膜区域中的图像进行极坐标变换来生成排序规则虹膜图案图像。 对照单元根据它们之间的相关性对照从注册图案生成单元输出的登记虹膜图案图像和从核对图案生成单元输出的对照光圈图案图像。

公开(公告)号：US20060221685A1

公开(公告)日：2006-10-05

申请号：US11418017

申请日：2006-05-05

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.