公开(公告)号：US06747529B2

公开(公告)日：2004-06-08

申请号：US10235785

申请日：2002-09-06

Applicant: Kazuhide Abe ,  Naoko Yanase ,  Takaaki Yasumoto ,  Ryoichi Ohara ,  Tatsuo Shimizu ,  Takashi Kawakubo

Inventor： Kazuhide Abe ,  Naoko Yanase ,  Takaaki Yasumoto ,  Ryoichi Ohara ,  Tatsuo Shimizu ,  Takashi Kawakubo

IPC: H03H915

CPC classification number: H03H9/176 ,  H03B5/366 ,  H03H9/173 ,  H03H9/175

Abstract: A piezoelectric thin film resonator which comprises a first electrode, a second electrode, and a piezoelectric film which is interposed between the first electrode and the second electrode, and formed of an epitaxial ferroelectric thin film containing barium titanate, a spontaneous polarization of the epitaxial ferroelectric thin film being uniaxially orientated in a direction normal to a film surface.

Abstract translation: 一种压电薄膜谐振器，其包括插入在第一电极和第二电极之间的第一电极，第二电极和压电膜，并且由包含钛酸钡的外延强电介质薄膜形成，外延强电介质的自发极化 薄膜在垂直于膜表面的方向上单轴取向。

公开(公告)号：US06198652B1

公开(公告)日：2001-03-06

申请号：US09289940

申请日：1999-04-13

Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

IPC: G11C1122

CPC classification number: H01L27/11502 ,  G11C11/22 ,  G11C11/223

Abstract: A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.

Abstract translation: 半导体集成存储器件包括以矩阵形式形成的多个存储器单元块，每个存储单元块包括：包括多个单元的存储单元链，每个单元包括铁电存储电容器和连接在其上的控制晶体管 平行于 包括参考电容器和与其并联连接的控制晶体管的单元的参考电容器; 读取晶体管，其具有连接到存储器单元链和参考单元之间的连接点的栅电极; 以及用于调整作为存储电容器的第一电极，参考电容器的第三电极和读取晶体管的连接点的存储节点的电位的控制晶体管。 利用这种结构，能够容易地制造半导体集成存储器件，以稳定地保持铁电极化并缩小。

公开(公告)号：US5796648A

公开(公告)日：1998-08-18

申请号：US762923

申请日：1996-12-10

Applicant: Takashi Kawakubo ,  Kazuhide Abe

Inventor： Takashi Kawakubo ,  Kazuhide Abe

IPC: H01L27/04 ,  G11C11/22 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11507 ,  H01L28/60

Abstract: A nonvolatile semiconductor memory device has a ferroelectric cell and a paraelectric cell. The ferroelectric cell includes a first thin-film capacitor which has a first lower electrode formed on a substrate, a first dielectric film grown on the first lower electrode and a first upper electrode formed on the first dielectric film, and a first switching transistor connected to the first thin-film capacitor. The paraelectric cell includes a second thin-film capacitor which has a second lower electrode, a second dielectric film grown on the second lower electrode and a second upper electrode formed on the second dielectric film, and a second switching transistor connected to the second thin-film capacitor. The first lower electrode is provided such that the first dielectric film has ferroelectricities, while the second lower electrode is provided such that the second dielectric film has paraelectricities.

Abstract translation: 非易失性半导体存储器件具有铁电电池和顺电池。 铁电单元包括：第一薄膜电容器，其具有形成在基板上的第一下电极，在第一下电极上生长的第一电介质膜和形成在第一电介质膜上的第一上电极;以及第一开关晶体管， 第一个薄膜电容器。 顺电池包括第二薄膜电容器，其具有第二下电极，在第二下电极上生长的第二电介质膜和形成在第二电介质膜上的第二上电极，以及连接到第二薄膜电容器的第二开关晶体管， 薄膜电容器。 第一下电极被设置为使得第一电介质膜具有铁电性，而第二下电极被设置为使得第二电介质膜具有顺电性。

公开(公告)号：US5739563A

公开(公告)日：1998-04-14

申请号：US559945

申请日：1995-11-17

Applicant: Takashi Kawakubo ,  Kenya Sano ,  Kazuhide Abe ,  Shuichi Komatsu ,  Noburu Fukushima ,  Kazuhiro Eguchi

Inventor： Takashi Kawakubo ,  Kenya Sano ,  Kazuhide Abe ,  Shuichi Komatsu ,  Noburu Fukushima ,  Kazuhiro Eguchi

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/94 ,  H01L27/108

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A semiconductor memory device comprising a silicon substrate, a plurality of switching transistors formed on the silicon substrate, an insulating layer having an opening and formed on a surface portion of the silicon substrate where the plurality of switching transistors formed, and a plurality of capacitors for accumulating electric charge formed on the insulating layer and connected respectively to the switching transistors via a conductive film buried in the opening of insulating layer, wherein each of the capacitors for accumulating electric charge is provided with an underlying crystal layer formed on the insulating layer and with a dielectric film consisting essentially of a ferroelectric material and epitaxially or orientationaly grown on the underlying crystal layer, and the switching transistors and the capacitors for accumulating electric charge connected to each other constitute a plurality of memory cells arranged in a two-dimensional pattern.

Abstract translation: 一种半导体存储器件，包括硅衬底，形成在硅衬底上的多个开关晶体管，具有开口并形成在形成有多个开关晶体管的硅衬底的表面部分上的绝缘层，以及多个用于 累积形成在绝缘层上的电荷，并且经由埋在绝缘层开口中的导电膜分别连接到开关晶体管，其中用于积累电荷的每个电容器设置有形成在绝缘层上的下面的晶体层， 基本上由铁电材料构成并在下面的晶体层上生长的外延或取向的电介质膜，并且用于积累彼此连接的电荷的开关晶体管和电容器构成以二维图案布置的多个存储单元。

公开(公告)号：US5691219A

公开(公告)日：1997-11-25

申请号：US527581

申请日：1995-09-13

Applicant: Takashi Kawakubo ,  Kazuhiro Eguchi ,  Shuichi Komatsu ,  Kazuhide Abe

Inventor： Takashi Kawakubo ,  Kazuhiro Eguchi ,  Shuichi Komatsu ,  Kazuhide Abe

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L28/55 ,  H01L27/10808 ,  H01L28/91 ,  H01L27/10852 ,  Y10S148/014

Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.

Abstract translation: 具有半导体衬底，设置在衬底上的绝缘层和存储单元的半导体存储器件。 存储单元具有设置在基板上的开关晶体管和在绝缘层中形成的沟槽中的电荷存储元件。 电荷存储元件具有下列顺序的底电极，电介质层和顶电极。

公开(公告)号：US5517445A

公开(公告)日：1996-05-14

申请号：US784073

申请日：1991-10-30

Applicant: Motomasa Imai ,  Kazuhide Abe ,  Koji Yamakawa ,  Hiroshi Toyoda ,  Yoshiko Kohanawa ,  Mitsuo Harata

Inventor： Motomasa Imai ,  Kazuhide Abe ,  Koji Yamakawa ,  Hiroshi Toyoda ,  Yoshiko Kohanawa ,  Mitsuo Harata

IPC: G11C11/22 ,  G11C17/04

CPC classification number: G11C11/22

Abstract: A non-volatile semiconductor memory device, includes a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, the semiconductor layer and the ferroelectric layer forming a semiconductor-ferroelectric junction, a writing circuit in which a voltage higher than a coercive electric field of the ferroelectric material is applied to the capacitor of the memory cell to align a polarization direction of the ferroelectric layer in a predetermined direction so as to set a capacitance of the capacitor at a predetermined value, thereby writing data corresponding to the predetermined value of the capacitance, and a reading circuit in which a voltage less than the coercive electric field of the ferroelectric layer is applied to the capacitor of the memory cell in which the data is written, thereby reading the data.

Abstract translation: 一种非易失性半导体存储器件，包括具有电容器的存储单元，所述电容器通过在一对电极之间堆叠半导体层和铁电层而形成，所述半导体层和形成半导体 - 铁电结的铁电层，其中写入电路 将高于铁电材料的矫顽电场的电压施加到存储单元的电容器，以将铁电层的偏振方向沿预定方向对齐，以将电容器的电容设置在预定值，从而写入 对应于电容的预定值的数据，以及读取电路，其中将低于铁电层的矫顽电场的电压施加到其中写入数据的存储单元的电容器，从而读取数据。

公开(公告)号：US5297077A

公开(公告)日：1994-03-22

申请号：US676546

申请日：1991-03-28

Applicant: Motomasa Imai ,  Hiroshi Toyoda ,  Kazuhide Abe ,  Koji Yamakawa ,  Hisakazu Iizuka ,  Mitsuo Harata ,  Koji Sakui

Inventor： Motomasa Imai ,  Hiroshi Toyoda ,  Kazuhide Abe ,  Koji Yamakawa ,  Hisakazu Iizuka ,  Mitsuo Harata ,  Koji Sakui

IPC: G11C11/22 ,  G11C14/00

CPC classification number: G11C14/00 ,  G11C11/22

Abstract: A semiconductor memory device comprises a ferroelectric capacitor, a voltage output circuit for outputting a first voltage for reversely polarizing the ferroelectric capacitor and a second voltage by which the polarization of the ferroelectric capacitor is not reversed, regardless of data stored in the ferroelectric capacitor, a first reference capacitor having a such a capacitance as to accumulate less charge than charge which the ferroelectric capacitor accumulates, when the second voltage is applied to the ferroelectric capacitor, a second reference capacitor having such a capacitance that as to accumulate greater charge than the charge which the ferroelectric capacitor accumulates while the ferroelectric capacitor is forwardly polarized, when the first voltage is applied to the ferroelectric capacitor, thus reversely polarizing the ferroelectric capacitor, a sense amplifier connected to the ferroelectric capacitor and the first or second reference capacitor, a reference-capacitor selecting circuit for connecting the first reference capacitor to the sense amplifier when the voltage output circuit outputs the second voltage, and connecting the second reference capacitor to the sense amplifier while the voltage output circuit outputs the first voltage, and a circuit for determining data from the presence or absence of an electric charge in the ferroelectric capacitors while the memory is set in volatile mode, and for determining data from the direction in which the ferroelectric capacitor is polarized, while the memory is set in nonvolatile mode.

Abstract translation: 半导体存储器件包括铁电电容器，用于输出用于使强电介质电容器反向极化的第一电压的电压输出电路和强电介质电容器的极化不反转的第二电压，而与铁电电容器中存储的数据无关 第一参考电容器具有这样的电容，即当第二电压被施加到铁电电容器时，积累比铁电电容器累积的电荷少的电荷，第二参考电容器具有这样的电容，以便积累比电荷更大的电荷 当铁电电容器向前偏振时，铁电电容器累积，当第一电压施加到铁电电容器时，从而使铁电电容器反向极化，连接到铁电电容器和第一或第二参考电容器的读出放大器，参考电容器 s 选择电路，用于当电压输出电路输出第二电压时将第一参考电容器连接到读出放大器，并且在电压输出电路输出第一电压时将第二参考电容器连接到读出放大器;以及电路，用于从 当存储器被设置为易失性模式时，铁电电容器中存在或不存在电荷，并且用于从存储器设置为非易失性模式时从铁电电容器被极化的方向确定数据。

公开(公告)号：US4958327A

公开(公告)日：1990-09-18

申请号：US238399

申请日：1988-08-31

Applicant: Shiroh Saitoh ,  Mamoru Izumi ,  Syuzi Suzuki ,  Kazuhide Abe

Inventor： Shiroh Saitoh ,  Mamoru Izumi ,  Syuzi Suzuki ,  Kazuhide Abe

IPC: A61B8/00 ,  B06B1/06 ,  G01N29/04 ,  G01N29/24 ,  H04R3/00

CPC classification number: B06B1/064 ,  Y10S367/903

Abstract: An ultrasonic imaging apparatus includes an ultrasonic transducer for outputting an ultrasonic beam and converting the echo of the ultrasonic beam into an echo signal, a transmitter section for supplying a drive signal to the ultrasonic transducer, a receiver section for receiving the echo signal output from the ultrasonic transducer and converting the echo signal into an image signal, and a coaxial cable for coupling the ultrasonic transducer to the transmitter and receiver sections. The ultrasonic transducer is constituted by a two-layer ultrasonic transducer having an impedance smaller than an impedance of the coaxial cable.

Abstract translation: 超声波成像装置包括超声波换能器，用于输出超声波束并将超声波束的回波转换成回波信号;发送器部，用于向超声波换能器提供驱动信号;接收部，用于接收来自超声波束的回波信号 超声波换能器并将回波信号转换成图像信号，以及用于将超声换能器耦合到发射器和接收器部分的同轴电缆。 超声波换能器由具有比同轴电缆的阻抗小的阻抗的​​双层超声换能器构成。

公开(公告)号：US08859426B2

公开(公告)日：2014-10-14

申请号：US12170458

申请日：2008-07-10

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/768 ,  H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract translation: 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US08513715B2

公开(公告)日：2013-08-20

申请号：US12873788

申请日：2010-09-01

Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/41758 ,  H01L29/4238 ,  H03B5/326

Abstract: According to an embodiment, the present invention provides a semiconductor device that is easily integrated with other electronic circuits and functions as an oscillator with high frequency accuracy. The semiconductor device includes: a semiconductor substrate; an element region; an element isolation region that surrounds the element region; a field effect transistor including a gate electrode that is formed on the element region, source and drain regions, and a channel region that is interposed between the source region and the drain region; gate, source, and drain terminals that are used to apply a voltage to the gate electrode, the source region, and the drain region, respectively; and an output terminal that is electrically connected to the channel region. When the threshold voltage of the field effect transistor is Vth, a gate voltage Vgs applied between the source terminal and the gate terminal and a drain voltage Vds applied between the source terminal and the drain terminal satisfy the following relationship: Vth

Abstract translation: 根据实施例，本发明提供一种与其他电子电路容易集成并且作为高频精度的振荡器起作用的半导体器件。 半导体器件包括：半导体衬底; 元素区域 围绕元件区域的元件隔离区域; 场效应晶体管，其包括形成在所述元件区域，源极和漏极区域上的栅极电极以及介于所述源极区域和所述漏极区域之间的沟道区域; 栅极，源极和漏极端子，分别用于向栅极电极，源极区域和漏极区域施加电压; 以及电连接到沟道区的输出端子。 当场效应晶体管的阈值电压为Vth时，施加在源极端子和栅极端子之间的栅极电压Vgs和施加在源极端子和漏极端子之间的漏极电压Vds满足以下关系：Vth