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100 条记录 (耗时 0.034 秒)

    Reconfigurable logic devices
    84.
    发明授权
    Reconfigurable logic devices 有权
    可重构逻辑器件

    公开(公告)号：US08497703B2

    公开(公告)日：2013-07-30

    申请号：US13080938

    申请日：2011-04-06

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    IPC分类号： G06F7/38

    CPC分类号： H03K19/17752 ,  H03K19/17756

    摘要： Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.

    摘要翻译： 示例性实施例提供了一种可重新配置逻辑设备，其包括具有第一逻辑块和第二逻辑块的至少两个逻辑块，包括连接到第一逻辑块的至少多个第一全局线的全局线组和多个第二全局线 连接到第二逻辑块，以及全局控制器，其包括与至少一个第一全局线和一个第二全局线相关联的多个第一非易失性存储器件，所述全局控制器被配置为基于多个第一和第二全局线， 存储在相关联的第一非易失性存储器件中的第一数据。

    Ferroelectric memory devices and operating methods thereof
    85.
    发明授权
    Ferroelectric memory devices and operating methods thereof 有权
    铁电存储器件及其操作方法

    公开(公告)号：US08385098B2

    公开(公告)日：2013-02-26

    申请号：US12923131

    申请日：2010-09-03

    申请人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/11597 ,  H01L27/1203 ,  H01L29/1606 ,  H01L29/78391

    摘要： A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.

    摘要翻译： 具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。 通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

    Information storage devices including vertical nano wires
    88.
    发明授权
    Information storage devices including vertical nano wires 失效
    信息存储设备包括垂直纳米线

    公开(公告)号：US08089797B2

    公开(公告)日：2012-01-03

    申请号：US12659515

    申请日：2010-03-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    IPC分类号： G11C19/00

    CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

    摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

    Flat lamp using plasma discharge
    89.
    发明授权
    Flat lamp using plasma discharge 失效
    平板灯使用等离子体放电

    公开(公告)号：US07999474B2

    公开(公告)日：2011-08-16

    申请号：US12585972

    申请日：2009-09-30

    申请人： Young-dong Lee ,  Hidekazu Hatanaka ,  Seung-hyun Son ,  Jai-kwang Shin ,  Young-mo Kim

    发明人： Young-dong Lee ,  Hidekazu Hatanaka ,  Seung-hyun Son ,  Jai-kwang Shin ,  Young-mo Kim

    IPC分类号： H01J17/49

    CPC分类号： H01J11/40 ,  H01J11/12 ,  H01J11/28 ,  H01J11/38 ,  H01J61/54

    摘要： A plasma-discharge light emitting device is provided. The plasma-discharge light emitting device may include: rear and front panels separated from each other in a predetermined interval, wherein at least one discharge cell may be provided between the rear and front panels, and wherein plasma discharge may be generated in the discharge cells; a pair of discharge electrodes provided on at least one of the rear and front panels for each of the discharge cells; a trench provided as a portion of each of the discharge cells between the pair of the discharge electrodes; and electron-emitting material layers provided on both sidewalls of the trench.

    摘要翻译： 提供了一种等离子体放电发光器件。 等离子体放电发光器件可以包括：以预定间隔彼此分开的后面板和前面板，其中可以在后面板和前面板之间设置至少一个放电单元，并且其中可以在放电单元中产生等离子体放电 ; 一对放电电极，设置在每个放电单元的后面板和前面板中的至少一个上; 设置在所述一对放电电极之间的每个放电单元的一部分的沟槽; 以及设置在沟槽的两个侧壁上的电子发射材料层。