公开(公告)号：US20080071951A1

公开(公告)日：2008-03-20

申请号：US11929985

申请日：2007-10-30

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/00

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitting means for transmitting transmit data to an external signal line and a storing means for storing a first value representative of a transmit phase adjustment that is used to adjust when the transmit data is transmitted by the transmitting means. The first value is determined based on information stored in a memory device external to the integrated circuit device.

Abstract translation: 集成电路装置包括：发送装置，用于向外部信号线发送发送数据;以及存储装置，用于存储代表发送相位调整的第一值，该发送相位调整用于当发送装置发送发送数据时进行调整。 基于存储在集成电路装置外部的存储装置中的信息来确定第一值。

公开(公告)号：US20080052434A1

公开(公告)日：2008-02-28

申请号：US11929980

申请日：2007-10-30

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/00

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device. The value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line. The signals present on the external signal line comprise one selected from residual signals and cross coupled signals.

Abstract translation: 集成电路装置包括具有用于输出数据的输出驱动器的发送器电路和用于存储代表输出驱动器的均衡系数设置的值的寄存器。 该值可以基于存储在补充存储器件中的信息来确定。 该值表示补偿外部信号线上存在的信号的均衡系数设置。 存在于外部信号线上的信号包括从残留信号和交叉耦合信号中选择的信号。

公开(公告)号：US20070252074A1

公开(公告)日：2007-11-01

申请号：US11576438

申请日：2005-09-30

Applicant: Yi-Ren Ng ,  Patrick Hanrahan ,  Marc Levoy ,  Mark Horowitz

Inventor： Yi-Ren Ng ,  Patrick Hanrahan ,  Marc Levoy ,  Mark Horowitz

IPC: H01L27/00

CPC classification number: H04N5/2254 ,  G02B3/0056 ,  G02B27/0075 ,  H01L27/14627 ,  H04N5/2173 ,  H04N5/23212 ,  H04N5/23232 ,  H04N5/23293 ,  H04N13/236

Abstract: Image data is processed to facilitate focusing and/or optical correction. According to an example embodiment of the present invention, an imaging arrangement collects light data corresponding to light passing through a particular focal plane. The light data is collected using an approach that facilitates the determination of the direction from which various portions of the light incident upon a portion of the focal plane emanate from. Using this directional information in connection with value of the light as detected by photosensors, an image represented by the light is selectively focused and/or corrected.

Abstract translation: 处理图像数据以便于聚焦和/或光学校正。 根据本发明的示例性实施例，成像装置收集对应于通过特定焦平面的光的光数据。 使用有助于确定入射到焦平面的一部分上的光的各个部分的方向的方法来收集光数据。 使用与由光电传感器检测到的光的值相关联的该方向信息，由光表示的图像被选择性地聚焦和/或校正。

公开(公告)号：US20070239914A1

公开(公告)日：2007-10-11

申请号：US11672018

申请日：2007-02-06

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/00

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.

Abstract translation: 描述集成电路器件。 集成电路装置包括具有用于输出数据的输出驱动器的发送器电路和用于存储表示输出驱动器的均衡均衡设置的值的寄存器。 该值可以基于存储在补充存储器件中的信息来确定。

公开(公告)号：US20060224339A1

公开(公告)日：2006-10-05

申请号：US11445702

申请日：2006-06-02

Applicant: Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

Inventor： Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

IPC: G01R13/00

CPC classification number: H03L7/0814 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/044 ,  H04L7/10

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

公开(公告)号：US20060186915A1

公开(公告)日：2006-08-24

申请号：US11393104

申请日：2006-03-29

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: H03K19/003

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

公开(公告)号：US07076377B2

公开(公告)日：2006-07-11

申请号：US10429514

申请日：2003-05-05

Applicant: Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

Inventor： Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

IPC: G06F19/00

CPC classification number: H03L7/0814 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/044 ,  H04L7/10

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract translation: 电路，装置和方法使用相移数据采样时钟在接收电路获得系统余量，同时允许CDR在实施例中与输入数据流保持同步。 在一个实施例中，电路包括第一和第二采样器，用于对数据信号进行采样，并响应于数据时钟信号和边沿时钟信号输出数据和边缘信息。 相位检测器响应于数据信息和边缘信息产生相位信息。 时钟相位调整电路在同步模式期间响应于数据信息产生数据时钟信号和边沿时钟信号。 时钟相位调整电路在波形捕获模式期间递增数据时钟信号的相位。

公开(公告)号：US20060136153A1

公开(公告)日：2006-06-22

申请号：US11354964

申请日：2006-02-16

Applicant: Haw-Jyh Liaw ,  Xiangchao Yuan ,  Mark Horowitz

Inventor： Haw-Jyh Liaw ,  Xiangchao Yuan ,  Mark Horowitz

IPC: G01R15/00

CPC classification number: G01R31/31708 ,  G01R23/16 ,  G01R23/20 ,  G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/50012 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5004 ,  H04B17/309

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

公开(公告)号：US20060120409A1

公开(公告)日：2006-06-08

申请号：US11327213

申请日：2006-01-05

Applicant: Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

Inventor： Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

IPC: H04J3/06

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

公开(公告)号：US20050243612A1

公开(公告)日：2005-11-03

申请号：US11153679

申请日：2005-06-15

Applicant: Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

Inventor： Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

Abstract: At page 54, please delete the current abstract and replace it with the following: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

Abstract translation: 在第54页，请删除当前的摘要并将其替换为以下内容：集成电路存储器件包括使用第一控制信号加载地址的锁存电路。 第一控制信号的第一信号电平转换用于加载地址。 存储器阵列将数据存储在基于地址的存储器位置。 输出缓冲器在从第一信号电平转换起的一段时间后输出数据。 寄存器存储指定至少第一模式和第二模式之间的值。 当该值指定第一模式时，输出缓冲器响应于在第一信号电平转换之后发生的地址转换而输出该数据。 当该值指定第二模式时，输出缓冲器相对于外部时钟信号同步地输出数据。