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    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    81.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES
    82.
    发明公开
    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20240331781A1

    公开(公告)日：2024-10-03

    申请号：US18744335

    申请日：2024-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

    Multi-step pre-read for write operations in memory devices
    83.
    发明授权
    Multi-step pre-read for write operations in memory devices 有权

    公开(公告)号：US12106803B2

    公开(公告)日：2024-10-01

    申请号：US17824776

    申请日：2022-05-25

    Applicant: Micron Technology, Inc.

    Inventor： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

    IPC: G11C11/4074 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0076

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

    Memory device having shared access line for 2-transistor vertical memory cell
    85.
    发明授权
    Memory device having shared access line for 2-transistor vertical memory cell 有权

    公开(公告)号：US12069853B2

    公开(公告)日：2024-08-20

    申请号：US17712674

    申请日：2022-04-04

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/01

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

    MEMORY DEVICE HAVING TIERS OF 2-TRANSISTOR MEMORY CELLS
    86.
    发明公开
    MEMORY DEVICE HAVING TIERS OF 2-TRANSISTOR MEMORY CELLS 审中-公开

    公开(公告)号：US20240188273A1

    公开(公告)日：2024-06-06

    申请号：US18521273

    申请日：2023-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Karthik Sarpatwari

    IPC: H10B12/00 ,  G11C11/405 ,  G11C11/4096

    CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/4096

    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.

    Dirty write on power off
    87.
    发明授权
    Dirty write on power off 有权

    公开(公告)号：US11923007B2

    公开(公告)日：2024-03-05

    申请号：US18049855

    申请日：2022-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0038

    Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE
    88.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE 审中-公开

    公开(公告)号：US20240047356A1

    公开(公告)日：2024-02-08

    申请号：US18234602

    申请日：2023-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L23/528 ,  H01L29/24 ,  G11C5/06 ,  H10B12/00

    CPC classification number: H01L23/5286 ,  H01L29/24 ,  G11C5/063 ,  H10B12/01 ,  H10B12/20

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

    Accessing a multi-level memory cell
    89.
    发明授权
    Accessing a multi-level memory cell 有权

    公开(公告)号：US11894078B2

    公开(公告)日：2024-02-06

    申请号：US17825941

    申请日：2022-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

    IPC: G11C16/30 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

    Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

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