公开(公告)号：US09893083B1

公开(公告)日：2018-02-13

申请号：US15293133

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/06 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/033 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/7883

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20170301685A1

公开(公告)日：2017-10-19

申请号：US15133119

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US09773805B1

公开(公告)日：2017-09-26

申请号：US15187632

申请日：2016-06-20

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L29/51 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US09153455B2

公开(公告)日：2015-10-06

申请号：US13921509

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

IPC: H01L29/788 ,  H01L21/308 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/788

Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和具有基本对准侧壁的封盖区域和在控制栅极区域下方的电荷结构。