公开(公告)号：US12198975B2

公开(公告)日：2025-01-14

申请号：US17444230

申请日：2021-08-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/146 ,  H01L31/028

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US12108678B2

公开(公告)日：2024-10-01

申请号：US17649470

申请日：2022-01-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H01L41/08 ,  H03H3/02 ,  H03H9/00 ,  H03H9/02 ,  H10N30/00 ,  H10N30/072

CPC classification number: H10N30/072 ,  H03H3/02 ,  H03H9/0009 ,  H03H9/02047 ,  H03H9/02574 ,  H10N30/708

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US20240266172A1

公开(公告)日：2024-08-08

申请号：US18004594

申请日：2021-06-08

Applicant: Commissariat À L'énergie Atomique Et Aux Énergies Alternatives ,  Soitec

Inventor： Frédéric Allibert ,  Didier Landru ,  Oleg Kononchuk ,  Eric Guiot ,  Gweltaz Gaudin ,  Julie Widiez ,  Franck Fournel

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/04 ,  H01L21/324 ,  H01L23/00

CPC classification number: H01L21/187 ,  H01L21/02016 ,  H01L21/0485 ,  H01L21/324 ,  H01L24/83 ,  H01L2224/83894 ,  H01L2224/83948 ,  H01L2924/10253 ,  H01L2924/10272

Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).

公开(公告)号：US20240071755A1

公开(公告)日：2024-02-29

申请号：US18261605

申请日：2021-12-23

Applicant: Soitec ,  Applied Materials Inc

Inventor： Oleg Kononchuk ,  Christophe Maleville ,  Isabelle Bertrand ,  Youngpil Kim ,  Chee Hoe Wong

IPC: H01L21/02 ,  H01L21/322 ,  H01L21/762 ,  H01L23/66

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/3225 ,  H01L21/76254 ,  H01L23/66

Abstract: A support substrate for a radiofrequency application comprises: —a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm·cm and strictly less than 500 ohm·cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, —an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm·cm, —a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm·cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

公开(公告)号：US11855120B2

公开(公告)日：2023-12-26

申请号：US17649982

申请日：2022-02-04

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

CPC classification number: H01L27/14685 ,  H01L21/76254 ,  H01L27/14625

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20230378931A1

公开(公告)日：2023-11-23

申请号：US18352972

申请日：2023-07-14

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H03H3/02 ,  H03H9/17 ,  H03H9/145 ,  H10N30/072 ,  H10N30/87 ,  H03H9/64 ,  A61B5/00 ,  H03H9/25 ,  H03H9/56 ,  A61B5/145 ,  A61B5/1459 ,  H03H3/04 ,  H03H9/13 ,  H10N39/00 ,  H03H3/10 ,  H10N30/085

CPC classification number: H03H9/02834 ,  H03H3/02 ,  H03H9/02102 ,  H03H9/17 ,  H03H9/145 ,  H10N30/072 ,  H10N30/87 ,  H03H9/6489 ,  A61B5/685 ,  H03H9/25 ,  H03H9/56 ,  A61B5/14546 ,  A61B5/1459 ,  H03H3/04 ,  H03H9/13 ,  H03H9/02574 ,  H10N39/00 ,  H03H3/10 ,  H10N30/085 ,  H03H2003/0407 ,  A61B2562/0204

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20230291377A1

公开(公告)日：2023-09-14

申请号：US17907245

申请日：2021-03-24

Applicant: Soitec

Inventor： Djamel Belhachemi ,  Thierry Barge ,  Oleg Kononchuk ,  Brice Tavel

IPC: H03H3/08 ,  H03H9/02

CPC classification number: H03H3/08 ,  H03H9/02559

Abstract: A process for manufacturing a piezoelectric structure for a radiofrequency device comprises providing a substrate of piezoelectric material, providing a carrier substrate, providing a dielectric bonding layer on the substrate of piezoelectric material, a step of joining the substrate of piezoelectric material to the carrier substrate via the dielectric bonding layer, and a thinning step for forming the piezoelectric structure, which comprises a layer of piezoelectric material joined to a carrier substrate via the dielectric bonding layer.

公开(公告)号：US20230238274A1

公开(公告)日：2023-07-27

申请号：US18192016

申请日：2023-03-29

Applicant: Soitec

Inventor： Arnaud Castex ,  Oleg Kononchuk

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/76251 ,  H01L27/1203

Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RE devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

公开(公告)号：US11626319B2

公开(公告)日：2023-04-11

申请号：US17090608

申请日：2020-11-05

Applicant: Soitec

Inventor： Arnaud Castex ,  Oleg Kononchuk

IPC: H01L21/322 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02

Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

公开(公告)号：US20220277988A1

公开(公告)日：2022-09-01

申请号：US17663898

申请日：2022-05-18

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.