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    Nonvolatile memory comprising mini wells at a floating potential
    81.
    发明授权
    Nonvolatile memory comprising mini wells at a floating potential 有权
    非易失性存储器包括浮动电位的微型阱

    公开(公告)号：US08940604B2

    公开(公告)日：2015-01-27

    申请号：US13786197

    申请日：2013-03-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: H01L21/336 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

    CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L27/11524 ,  H01L29/66825

    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.

    Abstract translation: 本公开涉及一种在半导体衬底上包括非易失性存储器的集成电路。 集成电路包括注入衬底深度的掺杂隔离层，隔离的导电沟槽到达隔离层并形成存储单元的选择晶体管的栅极，垂直于导电沟槽并到达隔离层的隔离沟槽，并且导线平行 到导电沟槽，在衬底上延伸并形成存储器单元的电荷累积晶体管的控制栅极。 隔离沟槽和隔离的导电沟槽限定了衬底中的多个微型阱，所述微型阱彼此电隔离，每个具有浮置电势并且包括两个存储单元。

    Protection of an integrated circuit
    82.
    发明授权
    Protection of an integrated circuit 有权

    公开(公告)号：US12205650B2

    公开(公告)日：2025-01-21

    申请号：US18173472

    申请日：2023-02-23

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Marco Bildgen

    IPC: G11C16/22 ,  G06F21/78 ,  G11C16/16 ,  H10B41/30

    Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

    PHYSICAL UNCLONABLE FUNCTION DEVICE AND METHOD
    83.
    发明申请
    PHYSICAL UNCLONABLE FUNCTION DEVICE AND METHOD 有权

    公开(公告)号：US20210303735A1

    公开(公告)日：2021-09-30

    申请号：US17199438

    申请日：2021-03-12

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: G06F21/75 ,  G11C7/10 ,  G06F21/72

    Abstract: An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

    Structure and method of forming a semiconductor device
    84.
    发明授权
    Structure and method of forming a semiconductor device 有权

    公开(公告)号：US10971633B2

    公开(公告)日：2021-04-06

    申请号：US16560810

    申请日：2019-09-04

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L29/861 ,  H01L27/07 ,  H01L29/788 ,  H01L29/66

    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

    Compact non-volatile memory device of the type with charge trapping in a dielectric interface
    85.
    发明授权
    Compact non-volatile memory device of the type with charge trapping in a dielectric interface 有权

    公开(公告)号：US10790293B2

    公开(公告)日：2020-09-29

    申请号：US16542511

    申请日：2019-08-16

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L27/11563 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11536

    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

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