公开(公告)号：US06642105B2

公开(公告)日：2003-11-04

申请号：US10131010

申请日：2002-04-24

申请人： Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

发明人： Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

IPC分类号： H01L21336

CPC分类号： H01L21/823462 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： A semiconductor device having multi-gate insulating layers and methods of fabricating the same are provided. The semiconductor device includes an isolation region disposed at a predetermined region of a semiconductor substrate. The isolation region defines at least one first active region and at least one second active region. The first active region is covered with a first gate insulating layer, and the second active region is covered with a second gate insulating layer which is thinner than the first gate insulating layer. Preferably, the top surface of the first gate insulating layer has the same height as the that of the second gate insulating layer. The isolation region is filled with an isolation layer which preferably covers the entire sidewalls of the first and second gate insulating layers. A typical method includes the step of selectively forming a first gate insulating layer at a predetermined region of a semiconductor substrate. A second gate insulating layer which is thinner than the first insulating layer is selectively formed at the surface of the semiconductor substrate adjacent to the first gate insulating layer. Preferably, the bottom surface of the first gate insulating layer is lower than that of the second gate insulating layer. The first and second gate insulating layers are covered with a conductive layer. The conductive layer, the first and second gate insulating layers, and the substrate are etched to form an isolation region, for example, a trench region, defining a first active region under the first gate insulating layer and a second active region under the second gate insulating. An isolation layer is formed in the trench region. The isolation layer preferably covers the entire sidewalls of the first and second gate insulating layers.

公开(公告)号：US08110499B2

公开(公告)日：2012-02-07

申请号：US12437390

申请日：2009-05-07

申请人： Dae-Hyuk Kang ,  Young-Hoo Kim ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Jae-Dong Lee ,  Dae-Hong Eom ,  Jeong-Nam Han

发明人： Dae-Hyuk Kang ,  Young-Hoo Kim ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Jae-Dong Lee ,  Dae-Hong Eom ,  Jeong-Nam Han

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/485 ,  H01L27/24 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.

摘要翻译： 可以在具有接触区域的物体上形成绝缘层。 绝缘层可以被部分蚀刻以形成暴露接触区域的开口。 可以在暴露的接触区域上形成包括硅和氧的材料层。 可以在包括硅和氧的材料层上形成金属层。 包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。 可以在金属氧化物硅化物层上形成导电层以填充开口。

公开(公告)号：US20120007018A1

公开(公告)日：2012-01-12

申请号：US13240271

申请日：2011-09-22

申请人： Jong-Won LEE ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Jae-Dong Lee

发明人： Jong-Won LEE ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Jae-Dong Lee

IPC分类号： C09K13/00 ,  B82Y30/00

CPC分类号： H01L21/31053 ,  C09G1/02 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/7851

摘要： Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water. The first agent includes poly(acrylic acid), The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.

摘要翻译： 提供了相对于氧化硅选择性研磨氮化硅的浆料组合物，研磨氮化硅层的方法和使用其制造半导体器件的方法。 浆料组合物包括用于降低氧化物抛光速率的第一试剂，磨料颗粒和水。 第一种试剂包括聚（丙烯酸）。在半导体制造过程中，浆料组合物可以具有相对于氧化硅的氮化硅的高抛光选择性，以选择性地研磨氮化硅层。

公开(公告)号：US08084344B2

公开(公告)日：2011-12-27

申请号：US12292195

申请日：2008-11-13

申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

公开(公告)号：US07932163B2

公开(公告)日：2011-04-26

申请号：US12029572

申请日：2008-02-12

申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

摘要： Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

摘要翻译： 间隔开的接合表面形成在第一基底上。 第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。 接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。 器件隔离区域可以形成为与半导体区域中的至少一个相邻。

公开(公告)号：US20100127398A1

公开(公告)日：2010-05-27

申请号：US12592042

申请日：2009-11-18

申请人： Young-Hoo Kim ,  Chang-Ki Hong ,  Jae-Dong Lee

发明人： Young-Hoo Kim ,  Chang-Ki Hong ,  Jae-Dong Lee

IPC分类号： H01L23/498

CPC分类号： H01L21/76831 ,  H01L21/76885 ,  H01L27/10855 ,  H01L27/10888

摘要： In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor.

摘要翻译： 在半导体器件的布线结构及其制造方法中，布线结构包括接触焊盘，接触插塞，间隔物和绝缘夹层图案。 接触垫电连接到基板的接触区域。 接触插头设置在接触垫上并且电连接到接触垫。 隔离物面向接触垫的上侧表面和接触插塞的侧壁。 绝缘夹层图案具有开口，接触插塞和间隔件设置在开口中。 布线结构的间隔件可以防止接触垫在形成要连接到电容器的接触插塞时被清洁溶液损坏。

公开(公告)号：US07718535B2

公开(公告)日：2010-05-18

申请号：US11984399

申请日：2007-11-16

申请人： Jaekwang Choi ,  Jae-Dong Lee ,  Chang-Ki Hong

发明人： Jaekwang Choi ,  Jae-Dong Lee ,  Chang-Ki Hong

IPC分类号： H01L21/306

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/7684

摘要： The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.

摘要翻译： 提供适用于涉及多晶硅层的化学机械抛光（CMP）的工艺的新的浆料组合物的本发明的示例性实施方案。 浆料组合物包括一种或多种非离子聚合物表面活性剂，其将在暴露的多晶硅表面上选择性地形成钝化层，以便抑制相对于氧化硅和氮化硅的多晶硅去除速率并提高抛光的基材的平面度。 示例性的表面活性剂包括环氧乙烷（EO）和环氧丙烷（PO）嵌段共聚物的烷基和芳基醇，并且可以以高达约5重量％的量存在于浆料组合物中，尽管更小的浓度可能是有效的。 其它浆料添加剂可以包括粘度调节剂，pH调节剂，分散剂，螯合剂和适于改变氮化硅和氧化硅的相对去除速率的胺或亚胺表面活性剂。

公开(公告)号：US07704828B2

公开(公告)日：2010-04-27

申请号：US11741639

申请日：2007-04-27

申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Sung-Il Cho

发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Sung-Il Cho

IPC分类号： H01L21/8242

CPC分类号： H01L28/91

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括形成用于形成存储电极的模具，在模具的开口的侧壁处形成牺牲隔离物，沿着开口的内部形成用于存储电极的导电膜，通过湿法蚀刻工艺移除模具， 牺牲隔离物，并且在存储电极上依次形成电介质膜和上电极。

公开(公告)号：US20100015801A1

公开(公告)日：2010-01-21

申请号：US12460318

申请日：2009-07-16

申请人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

发明人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

IPC分类号： H01L21/768

CPC分类号： H01L21/76888 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/24

摘要： A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.

摘要翻译： 插头包括第一绝缘中间层，钨图案和氧化钨图案。 第一绝缘中间层具有在基板上形成的接触孔。 钨图案形成在接触孔中。 钨图案具有比第一绝缘中间层的上表面低的顶表面。 氧化钨图案形成在接触孔和钨图案上。 氧化钨图案具有水平面。

公开(公告)号：US20080206985A1

公开(公告)日：2008-08-28

申请号：US11878508

申请日：2007-07-25

申请人： Chae-Iyoung Kim ,  Chang-Ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

发明人： Chae-Iyoung Kim ,  Chang-Ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7688 ,  Y10S438/947

摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

摘要翻译： 提供制造半导体器件的方法。 所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。 第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。 多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。 第一接触掩模层可以形成在第一区域中。 第一虚拟掩模层可以形成在第二区域中。 可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。 可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。 可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。