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    Pulse generation circuit and semiconductor device
    82.
    发明授权
    Pulse generation circuit and semiconductor device 有权
    脉冲发生电路和半导体器件

    公开(公告)号：US09041453B2

    公开(公告)日：2015-05-26

    申请号：US14221523

    申请日：2014-03-21

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hiroyuki Miyake ,  Kouhei Toyotaka

    IPC: H03K3/00 ,  G06F1/04 ,  H03K3/356 ,  G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0404 ,  G09G2300/0413 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28 ,  H03K3/356026

    Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

    Abstract translation: 在像素部分的左侧和右侧设置两个包括移位寄存器和包括单导电型晶体管的解复用器的栅极驱动器。 栅极线在每M行中交替连接到左侧和右侧栅极驱动器。 移位寄存器包括串联连接的k个第一单元电路。 解复用器包括k个第二单位电路，其中每个电路从第一单元电路输入信号，并且连接M个栅极线。 第二单元电路选择在M个栅极线之间输出来自第一单位电路的输入信号的一个或多个布线，并将来自第一单元电路的信号输出到所选择的布线。 由于门信号可以从一级移位寄存器的输出输出到M条栅极线，所以移位寄存器的宽度可以变窄。

    Flip-flop circuit, driver circuit, display panel, display device, input/output device, and data processing device
    83.
    发明授权
    Flip-flop circuit, driver circuit, display panel, display device, input/output device, and data processing device 有权

    公开(公告)号：US12243459B2

    公开(公告)日：2025-03-04

    申请号：US18096117

    申请日：2023-01-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kouhei Toyotaka ,  Kazunori Watanabe ,  Susumu Kawashima ,  Daisuke Kubota ,  Tetsuji Ishitani ,  Akio Yamashita

    IPC: G09G3/20 ,  G06F3/041

    Abstract: A flip-flop circuit is provided. A driver circuit is provided. The flip-flop circuit includes first to fifth input terminals and first to third output terminals, the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulation signal, and the fifth input terminal is supplied with a second pulse width modulation signal. The first output terminal supplies a first selection signal in response to the first pulse width modulation signal in a period from supply of the first trigger signal to supply of the second trigger signal, the first output terminal supplies the first selection signal in a period during which the batch selection signal is supplied, the second output terminal supplies a second selection signal in response to the second pulse width modulation signal in the period from the supply of the first trigger signal to the supply of the second trigger signal, and the third output terminal supplies a third trigger signal.

    Semiconductor device
    84.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12199106B2

    公开(公告)日：2025-01-14

    申请号：US18197785

    申请日：2023-05-16

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kouhei Toyotaka ,  Jun Koyama ,  Hiroyuki Miyake

    IPC: G11C19/00 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  H01L29/786 ,  G09G3/3266 ,  G09G3/3275

    Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

    Semiconductor device
    90.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11847942B2

    公开(公告)日：2023-12-19

    申请号：US17929034

    申请日：2021-02-10

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kouhei Toyotaka ,  Kiyotaka Kimura

    IPC: G09G3/36

    CPC classification number: G09G3/3666 ,  G09G3/3659 ,  G09G3/3688 ,  G09G2300/0828 ,  G09G2310/027

    Abstract: A semiconductor device using a pass transistor is provided. The semiconductor device includes a first circuit, a second circuit, a plurality of input terminals, and an output terminal. The first circuit includes a plurality of first transistors functioning as pass transistors, and the second circuit includes a plurality of second transistors functioning as pass transistors. Note that the number of the first transistors is larger than the number of the second transistors, a gate of the first transistor is supplied with a first signal, and a gate of the second transistor is supplied with a second signal. The first circuit is supplied with grayscale signals through x input terminals, and the first circuit selects y grayscale signals of the grayscale signals with the first signal. The second circuit is supplied with y (y

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