中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

218 records (took 0.028 seconds)

    Transitional interface between metal and dielectric in interconnect structures
    84.
    发明授权
    Transitional interface between metal and dielectric in interconnect structures 有权
    互连结构中金属和电介质之间的过渡界面

    公开(公告)号：US08349730B2

    公开(公告)日：2013-01-08

    申请号：US12823649

    申请日：2010-06-25

    Applicant: Chien-Hsueh Shih ,  Shau-Lin Shue

    Inventor： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC: H01L21/44 ,  H01L23/52

    CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    Abstract translation: 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。

    Apparatus for electrochemical plating semiconductor wafers
    85.
    发明授权
    Apparatus for electrochemical plating semiconductor wafers 有权
    电化学电镀半导体晶片的装置

    公开(公告)号：US08277619B2

    公开(公告)日：2012-10-02

    申请号：US13176839

    申请日：2011-07-06

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25B9/04 ,  C25B9/02 ,  C25D17/04 ,  C25D17/06

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: An electroplating apparatus for depositing a conductive material on a semiconductor wafer includes a vessel for holding an electroplating bath, a support for holding a semiconductor wafer within the vessel and beneath a surface of the bath; first and second electrodes within the vessel, between which an electrical current may flow causing conductive material to be electrolytically deposited onto the wafer, a third electrode disposed outside of the bath for applying a static electric charge to the wafer, and an electrical power supply coupled with the third electrode.

    Abstract translation: 用于在半导体晶片上沉积导电材料的电镀设备包括用于保持电镀槽的容器，用于将半导体晶片保持在容器内并在浴表面下方的支撑体; 容器内的第一和第二电极，电流可以在其间流动，导致导电材料被电解沉积到晶片上;第三电极，设置在电镀槽的外面，用于向晶片施加静电荷;以及电源， 与第三电极。

    Barrier material and process for Cu interconnect
    88.
    发明授权
    Barrier material and process for Cu interconnect 有权
    铜互连的阻挡材料和工艺

    公开(公告)号：US08178437B2

    公开(公告)日：2012-05-15

    申请号：US12181770

    申请日：2008-07-29

    Applicant: Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC: H01L21/4763

    CPC classification number: H01L21/76846 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

    Abstract translation: 描述了半导体扩散阻挡层及其制造方法。 阻挡层包括至少一层TaN，TiN，WN，TbN，VN，ZrN，CrN，WC，WN，WCN，NbN，AlN及其组合。 阻挡层还可以包括富金属表面。 实施例优选包括约10至500埃厚的胶层，由Ru，Ta，Ti，W，Co，Ni，Al，Nb，AlCu和富含金属的氮化物组成的胶层及其组合。 胶层厚度与阻挡层厚度的比率优选为约1〜50。其他优选实施方案还包括导体退火步骤。 可以使用PVD，CVD，PECVD，PEALD和/或ALD方法沉积各种层，包括氮化和硅化方法。

    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE
    89.
    发明申请
    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
    低电阻高可靠性接触半导体器件的金属线结构

    公开(公告)号：US20110024908A1

    公开(公告)日：2011-02-03

    申请号：US12845852

    申请日：2010-07-29

    Applicant: Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    Inventor： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC: H01L23/52 ,  H01L21/4763

    CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    Abstract translation: 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

Patent Agency Ranking