公开(公告)号：US07911023B2

公开(公告)日：2011-03-22

申请号：US12289772

申请日：2008-11-04

申请人： Nozomu Akagi ,  Hitoshi Yamaguchi ,  Tetsuo Fujii

发明人： Nozomu Akagi ,  Hitoshi Yamaguchi ,  Tetsuo Fujii

IPC分类号： H01L21/70

CPC分类号： H01L29/7813 ,  H01L22/14 ,  H01L27/0921 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766

摘要： A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other.

摘要翻译： 公开了一种半导体装置。 半导体装置包括具有彼此相对的第一表面和第二表面的半导体衬底。 半导体装置还包括多个双面电极元件，每个双面电极元件分别具有位于半导体衬底的第一和第二表面上的一对电极。 A电流在第一和第二电极之间流动。 每个双面电极元件具有位于半导体衬底中的PN列区域。 半导体装置还包括围绕多个双面电极元件中的每一个的绝缘沟槽，并且使多个双面电极元件彼此绝缘和分离。

公开(公告)号：US20100150677A1

公开(公告)日：2010-06-17

申请号：US12087875

申请日：2007-01-15

申请人： Hitoshi Yamaguchi

发明人： Hitoshi Yamaguchi

IPC分类号： B23G5/06 ,  B05D3/12 ,  B23P15/52

CPC分类号： B23P15/52 ,  B23G5/06 ,  B23G2200/26 ,  B23G2225/32 ,  B23G2225/52 ,  B23G2225/56 ,  B23G2225/60 ,  Y10T29/49826 ,  Y10T408/78 ,  Y10T408/9048

摘要： A rotary cutting tool is provided which is less likely to cause chips to get stuck, and which can be manufactured at a low cost.The rotary cutting tool includes a body having a relief surface (6) and a rake face (7) which is connected to the relief surface (6). An oxide film (9) is formed on the rake face (7) by oxidizing the surface of the body, and a hard film (8) is formed on the relief surface (6) and the oxide film (9). The hard film (8) is made of a metal carbide, a metal nitride, a metal carbonitride, or a solid solution thereof.

摘要翻译： 提供了一种旋转切削工具，其不太可能导致芯片被卡住，并且可以以低成本制造。 旋转切削工具包括具有与浮雕表面（6）连接的浮雕表面（6）和前刀面（7）的主体。 通过氧化本体的表面，在前刀面（7）上形成氧化物膜（9），在浮雕面（6）和氧化膜（9）上形成硬膜（8）。 硬膜（8）由金属碳化物，金属氮化物，金属碳氮化物或其固溶体构成。

公开(公告)号：US20090321819A1

公开(公告)日：2009-12-31

申请号：US12314786

申请日：2008-12-16

申请人： Yuma Kagata ,  Jun Sakakibara ,  Hitoshi Yamaguchi

发明人： Yuma Kagata ,  Jun Sakakibara ,  Hitoshi Yamaguchi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/66734

摘要： A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.

摘要翻译： 一种半导体器件包括：第一半导体层; PN列层，其具有第一和第二列层; 和第二半导体层。 第一和第二列层中的每一个包括与水平方向一起交替布置的第一和第二列。 通过从第一列中的杂质量减去第二列中的杂质量，第一和第二列层分别具有在预定深度处限定的第一和第二杂质量差异。 第一杂质量差为常数和正数。 第二杂质量差为常数和负数。

公开(公告)号：US20090321015A1

公开(公告)日：2009-12-31

申请号：US12304577

申请日：2007-06-18

申请人： Kohichiro Kawate ,  Hitoshi Yamaguchi ,  Noriko Kikuchi ,  Tomihiro Hara ,  Yoshiyuki Ohkura

发明人： Kohichiro Kawate ,  Hitoshi Yamaguchi ,  Noriko Kikuchi ,  Tomihiro Hara ,  Yoshiyuki Ohkura

IPC分类号： B32B7/12 ,  C08K5/3445

CPC分类号： C08K5/5442 ,  C08G65/336 ,  C08G2650/56 ,  C08L33/06 ,  C08L63/00 ,  C08L71/12 ,  C08L81/06 ,  C08L2666/22 ,  C09J171/00 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/83851 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/09701 ,  H05K3/305 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/0212 ,  Y02P70/613 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

摘要： To provide an adhesive composition which can exhibit high adhesion to a circuit board and also has ability capable of releasing the connection to the circuit board connected and reconnecting the circuit board (repairing properties). An adhesive composition comprising: (i) one or more aromatic-group-containing polyhydroxy ether resins, (ii) a compound having an alkoxysilyl group and an imidazole group in the molecule, and (iii) organic particles, wherein the content of the organic particles is 50% by weight or more based on the weight of the adhesive composition.

摘要翻译： 提供一种能够对电路板具有高粘附性的粘合剂组合物，并且还具有能够释放与连接并重新连接电路板的电路板的连接（修复特性）的能力。 一种粘合剂组合物，其包含：（i）一种或多种含芳族基团的多羟基醚树脂，（ii）分子中具有烷氧基甲硅烷基和咪唑基的化合物，和（iii）有机颗粒，其中有机 基于粘合剂组合物的重量，颗粒为50重量％以上。

公开(公告)号：US20090159963A1

公开(公告)日：2009-06-25

申请号：US12292351

申请日：2008-11-18

申请人： Hitoshi Yamaguchi ,  Tsuyoshi Yamamoto

发明人： Hitoshi Yamaguchi ,  Tsuyoshi Yamamoto

IPC分类号： H01L27/06

CPC分类号： H01L29/7815 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/7826

摘要： A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of first cells is coupled with a gate terminal of the second cell and a source terminal of the plurality of first cells is coupled with a source terminal of the second cell on a lower potential side. The resistor has a first terminal coupled with a drain terminal of the second cell and a second terminal coupled with a drain terminal of the first cells on a higher potential side. A gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor.

摘要翻译： 半导体器件包括绝缘栅晶体管和电阻器。 绝缘栅晶体管包括用于向负载提供电流的多个第一单元和用于检测在第一单元中流动的电流的第二单元。 所述多个第一单元的栅极端子与所述第二单元的栅极端子耦合，并且所述多个第一单元的源极端子与所述第二单元的源极端子耦合在较低电位侧。 电阻器具有与第二单元的漏极端子耦合的第一端子和与较高电位侧的第一单元的漏极端子耦合的第二端子。 绝缘栅极晶体管的栅极电压基于电阻器的电位进行反馈控制。

公开(公告)号：US20090121819A1

公开(公告)日：2009-05-14

申请号：US12289384

申请日：2008-10-27

申请人： Susumu Haratani ,  Hitoshi Yamaguchi

发明人： Susumu Haratani ,  Hitoshi Yamaguchi

IPC分类号： H01F17/02

CPC分类号： G01R33/09 ,  G01R33/091 ,  H01F5/003 ,  H01F38/14

摘要： A magnetic coupler having higher response is provided. The magnetic coupler includes a thin film coil wound in a first layer; a first MR element being disposed in a second layer, and detecting an induced magnetic field generated by a signal current flowing through the thin film coil; and yokes being disposed close to the first MR element, and including a soft magnetic material. The first MR element is disposed in a position corresponding to a linear region of the thin film coil in a stacking direction. The yokes are disposed at both of an inner turn side and an outer turn side of the thin film coil in a manner of interposing the first MR element in the second layer. Thus, reduction in intensity of the induced magnetic field is suppressed, and intensity distribution of the induced magnetic field becomes flatter.

摘要翻译： 提供了具有较高响应的磁耦合器。 磁耦合器包括缠绕在第一层中的薄膜线圈; 第一MR元件设置在第二层中，并且检测由流过薄膜线圈的信号电流产生的感应磁场; 并且轭设置成靠近第一MR元件，并且包括软磁材料。 第一MR元件被布置在与层叠方向上的薄膜线圈的线性区域对应的位置。 磁轭以将第一MR元件插入第二层的方式设置在薄膜线圈的内侧转弯侧和外侧转动侧。 因此，抑制感应磁场强度的降低，感应磁场的强度分布变得更平坦。

公开(公告)号：US20090032965A1

公开(公告)日：2009-02-05

申请号：US12216808

申请日：2008-07-10

申请人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

发明人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.

摘要翻译： 一种半导体器件包括：第一半导体层; 在第一半导体层上的p-n列部分，并且包括交替布置的第二和第三半导体层; 以及与p-n列部分相邻并包括第四半导体层的周边部分。 端部第二半导体层的杂质量等于或大于其它第二半导体层的一半。 第三半导体层包括与端部第二半导体层相邻的大杂质量部分。 大杂质量部分包括杂质量大于其它第三半导体层的杂质量的至少一个第三半导体层。

公开(公告)号：US20080246096A1

公开(公告)日：2008-10-09

申请号：US12078369

申请日：2008-03-31

申请人： Jun Sakakibara ,  Hitoshi Yamaguchi

发明人： Jun Sakakibara ,  Hitoshi Yamaguchi

IPC分类号： H01L27/06 ,  H01L21/329 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/32 ,  H01L29/7806 ,  H01L29/861

摘要： A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short.

摘要翻译： 半导体器件包括衬底，具有第一导电类型的多个第一列，具有第二导电类型的多个第二列，第一电极和第二电极。 第一列和第二列交替地布置在基板上以提供超连接结构。 第一电极设置在超结结构上，与第一列形成肖特基结，并与第二列形成欧姆结。 第二电极设置在超级结结构的相对侧上的衬底上。 衬底和超结结构的至少一部分具有晶格缺陷，以提供寿命控制区域，在该寿命期内少数载流子的寿命被控制为短。

公开(公告)号：US07345339B2

公开(公告)日：2008-03-18

申请号：US10872789

申请日：2004-06-22

申请人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

发明人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

摘要翻译： 半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。 身体区域设置在漂移区域上。 第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。 沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。 沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。 第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

公开(公告)号：US20080038850A1

公开(公告)日：2008-02-14

申请号：US11889075

申请日：2007-08-09

申请人： Hitoshi Yamaguchi ,  Takeshi Miyajima

发明人： Hitoshi Yamaguchi ,  Takeshi Miyajima

IPC分类号： H01L21/336 ,  H01L21/66

CPC分类号： H01L29/7813 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  Y10S438/977

摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

摘要翻译： 半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。 第一导电型层的杂质浓度比第一列高。 第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。