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141 条记录 (耗时 0.037 秒)

    Method of fabricating semiconductor structures for latch-up suppression
    82.
    发明授权
    Method of fabricating semiconductor structures for latch-up suppression 失效
    制造用于闭锁抑制的半导体结构的方法

    公开(公告)号：US07648869B2

    公开(公告)日：2010-01-19

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    Concurrent fin-fet and thick body device fabrication
    83.
    发明授权
    Concurrent fin-fet and thick body device fabrication 有权
    并发鳍和厚体器件制造

    公开(公告)号：US07473970B2

    公开(公告)日：2009-01-06

    申请号：US11481120

    申请日：2006-07-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

    摘要翻译： 集成电路芯片和半导体结构。 集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。

    Method and structure to process thick and thin fins and variable fin to fin spacing
    84.
    发明授权
    Method and structure to process thick and thin fins and variable fin to fin spacing 有权
    处理厚薄翅片和可变翅片翅片间距的方法和结构

    公开(公告)号：US07301210B2

    公开(公告)日：2007-11-27

    申请号：US11306827

    申请日：2006-01-12

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

    摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

    摘要翻译： 公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

    Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing
    85.
    发明授权
    Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing 失效
    用于通过在处理期间去除多晶硅栅极来产生自对准SOI二极管的方法

    公开(公告)号：US07138313B2

    公开(公告)日：2006-11-21

    申请号：US10708912

    申请日：2004-03-31

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66136 ,  H01L29/861

    摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

    摘要翻译： 一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层 结构体; 并移除保护结构。 该方法还包括在扩散区上形成硅化物层并与保护结构对准。 保护结构包括硬掩模，其中硬掩模包括氮化硅层。 或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。 此外，在去除步骤中，衬垫保留在衬底上。

    Method and structures for dual depth oxygen layers in silicon-on-insulator processes
    86.
    发明授权
    Method and structures for dual depth oxygen layers in silicon-on-insulator processes 有权
    硅绝缘体工艺中双重深度氧层的方法和结构

    公开(公告)号：US06774017B2

    公开(公告)日：2004-08-10

    申请号：US10190405

    申请日：2002-07-03

    申请人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Randy William Mann ,  Steven Howard Voldman

    发明人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Randy William Mann ,  Steven Howard Voldman

    IPC分类号： H01L2120

    CPC分类号： H01L27/1203 ,  H01L21/26533 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283

    摘要： A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

    摘要翻译： 一种半导体结构及其相关制造方法，包括具有连续掩埋氧化物层并具有多个沟槽隔离结构的衬底。 掩埋氧化物层可以位于衬底内的多于一个深度处。 沟槽隔离结构的几何形状可随深度而变化。 沟槽隔离结构可以接触或不接触埋入的氧化物层。 两个沟槽隔离结构可以将衬底穿透到相同的深度或不同的深度。 沟槽隔离结构在衬底内的区域之间提供绝缘分离，并且分离的区域可以包含半导体器件。 半导体结构便于在公共晶片上提供数字和模拟器件。 双深埋入氧化物层有利于非对称半导体结构。

    Semiconductor structure having heterogenous silicide regions having titanium and molybdenum
    88.
    发明授权
    Semiconductor structure having heterogenous silicide regions having titanium and molybdenum 失效
    具有异质硅化物区域的具有钛和钼的半导体结构

    公开(公告)号：US06512296B1

    公开(公告)日：2003-01-28

    申请号：US09636325

    申请日：2000-08-10

    申请人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

    发明人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

    IPC分类号： H01L2348

    CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/456

    摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

    摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

    Domino logic circuit having multiplicity of gate dielectric thicknesses
    89.
    发明授权
    Domino logic circuit having multiplicity of gate dielectric thicknesses 有权
    具有多个栅介质厚度的多米诺逻辑电路

    公开(公告)号：US06404236B1

    公开(公告)日：2002-06-11

    申请号：US09811967

    申请日：2001-03-19

    申请人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

    摘要翻译： 公开了具有时钟预充电的多米诺骨牌逻辑电路。 多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。 连接到电源，预充电晶体管接收时钟输入。 隔离晶体管连接到地，并接收时钟输入。 耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。 评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。