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    Silicon dot formation by direct self-assembly method for flash memory
    81.
    发明授权
    Silicon dot formation by direct self-assembly method for flash memory 有权
    通过闪存的直接自组装方法形成硅点

    公开(公告)号：US09281203B2

    公开(公告)日：2016-03-08

    申请号：US13974155

    申请日：2013-08-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L21/8239 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L21/28273 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32139 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements comprising a substantially equal size within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first or second polymer species is then removed resulting with a pattern of micro-domains or the polymer matrix with a pattern of holes, which may be utilized as a hard-mask to form a substantially identical pattern of discrete storage elements through an etch, ion implant technique, or a combination thereof.

    Abstract translation: 本公开的一些实施例涉及一种实现在存储器单元内包括基本相等尺寸的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后去除第一或第二聚合物物质，其具有微畴图案或具有空穴图案的聚合物基质，其可以用作硬掩模，以通过蚀刻形成基本相同的离散存储元件图案， 离子注入技术或其组合。

    Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method
    82.
    发明授权
    Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method 有权
    通过直接自组装方法形成垂直磁性随机存取存储器（MRAM）

    公开(公告)号：US09257636B2

    公开(公告)日：2016-02-09

    申请号：US14023552

    申请日：2013-09-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L43/12

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

    Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

    Uniformity Control for SI Dot Size in Flash Memory
    84.
    发明申请
    Uniformity Control for SI Dot Size in Flash Memory 审中-公开
    闪存中SI点大小的均匀性控制

    公开(公告)号：US20150311300A1

    公开(公告)日：2015-10-29

    申请号：US14261539

    申请日：2014-04-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

    IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

    CPC classification number: H01L21/02271 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42332

    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.

    Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成隧道氧化物。 在隧道氧化物上形成一层硅点成核。 硅点层包括具有根据第一尺寸分布而不同的各自的初始尺寸的硅点成核。 进行蚀刻处理以减小硅点成核的初始尺寸，因此尺寸减小的硅点成核具有根据第二尺寸分布而不同的相应减小的尺寸。 第二尺寸分布具有比第一尺寸分布更小的扩展。

    DEEP TRENCH CAPACITOR
    86.
    发明申请
    DEEP TRENCH CAPACITOR 有权
    深层电容电容

    公开(公告)号：US20140374880A1

    公开(公告)日：2014-12-25

    申请号：US13925984

    申请日：2013-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10829 ,  H01L24/73 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

    Abstract translation: 本公开涉及一种形成电容器结构的方法，包括在凹槽的底部和侧壁上沉积由多个氧化物/氮化物/氧化物（ONO）层隔开的多个均匀厚度的多个第一多晶硅（POLY）层，以及 基材表面。 第二POLY层沉积在多个第一POLY层上，被ONO层隔开，并填充凹槽的其余部分。 用第一化学机械抛光（CMP）去除第二POLY层和第二ONO层的部分。 多个第一POLY层和表面上不在电容器结构的掺杂区域内的第一ONO层的一部分用第一图案和蚀刻工艺去除，使得多个第一POLY层中的每一个的顶表面 第一POLY层被暴露以形成接触。

    Thick AlN inter-layer for III-nitride layer on silicon substrate
    88.
    发明授权
    Thick AlN inter-layer for III-nitride layer on silicon substrate 有权
    硅衬底上的III族氮化物层的厚AlN层间

    公开(公告)号：US08809910B1

    公开(公告)日：2014-08-19

    申请号：US13749819

    申请日：2013-01-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC: H01L31/072

    CPC classification number: H01L29/2003 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

    Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

    Abstract translation: 本公开涉及具有GaN和氮化铝（AlN）交替层的复合氮化镓层的氮化镓（GaN）晶体管器件。 在一些实施例中，GaN晶体管器件具有设置在半导体衬底之上的第一GaN层。 AlN层间设置在第一GaN层上。 第二GaN层设置在AlN层间。 AlN层间层允许GaN层的厚度在连续的GaN层上增加，减轻GaN衬底的弯曲和破裂，同时改善所公开的GaN器件的击穿电压。

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