公开(公告)号：US5289416A

公开(公告)日：1994-02-22

申请号：US820489

申请日：1992-01-14

申请人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

发明人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

IPC分类号： G11C11/401 ,  G06F11/20 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： H01L21/76894 ,  G11C29/83 ,  G11C29/832 ,  H01L21/76888 ,  G11C8/16

摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

摘要翻译： 提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。 由该预定布线整体形成的切割点或其一部分设置在该装置上。 通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。 此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。 布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。 利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。 这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

公开(公告)号：US5264743A

公开(公告)日：1993-11-23

申请号：US621064

申请日：1990-11-29

申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Hitoshi Tanaka ,  Yasushi Watanabe ,  Eiji Kume ,  Masanori Isoda ,  Eiji Yamasaki ,  Tatsumi Uchigiri

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  H03K19/00

CPC分类号： G11C7/1069 ,  G11C5/147 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1051 ,  G11C8/08

摘要： The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

摘要翻译： 本发明旨在以低电压高速运行半导体器件。 使用电路配置，其中根据是要读取还是写入信息，在公共I / O线和数据线之间的传输阻抗改变。 提供了一种电流/电压转换器，其包括与选择的MISFET不同的导电类型的MISFET。 因此，读取信息的速度增加。 提供具有高驱动能力的中间电压发生器。 因此，对具有大负载电容的LSI具有足够的驱动能力。 提供了一种电压转换器，其将数据线电源电压或字线电源电压转换为更高的电压。 因此，确保了稳定的信号传输。

公开(公告)号：US5179539A

公开(公告)日：1993-01-12

申请号：US865677

申请日：1992-04-08

申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Norio Miyake ,  Takaaki Noda ,  Jun Etoh ,  Hitoshi Tanaka ,  Shin'ichi Ikenaga

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02

CPC分类号： G11C5/147 ,  G05F1/465 ,  G05F3/245 ,  G05F3/247 ,  G11C11/4074 ,  H01L27/0203

摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

摘要翻译： 涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。 可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。 提供了改进的测试这些电路的方法。

公开(公告)号：US4942556A

公开(公告)日：1990-07-17

申请号：US377181

申请日：1989-07-10

申请人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

发明人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

IPC分类号： G11C15/04 ,  G11C29/00 ,  G11C29/44

CPC分类号： G11C29/76 ,  G11C15/04 ,  G11C15/046 ,  G11C29/44

摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

摘要翻译： 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

公开(公告)号：US4709350A

公开(公告)日：1987-11-24

申请号：US627895

申请日：1984-07-05

申请人： Yoshinobu Nakagome ,  Masakazu Aoki ,  Masashi Horiguchi ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

发明人： Yoshinobu Nakagome ,  Masakazu Aoki ,  Masashi Horiguchi ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

IPC分类号： G11C14/00 ,  G11C11/56 ,  G11C19/00 ,  G11C27/00

CPC分类号： G11C19/00 ,  G11C11/565 ,  G11C8/04

摘要： In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.

摘要翻译： 在通过将包括电容元件和一个MOS-FET的多个存储单元布置在矩阵中的用于在XY地址系统中读取和写入存储电荷的半导体存储器中，本发明公开了一种使用多级存储结构进行读取和 通过对电容器的平板电极或MOS-FET的栅电极施加多电平阶梯电压以写入和读取信号电荷，写入存储在电容元件中的至少两个多电平数据。

公开(公告)号：US07688670B2

公开(公告)日：2010-03-30

申请号：US12165681

申请日：2008-07-01

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

公开(公告)号：US07411856B2

公开(公告)日：2008-08-12

申请号：US11727430

申请日：2007-03-27

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

公开(公告)号：US07411855B2

公开(公告)日：2008-08-12

申请号：US11727429

申请日：2007-03-27

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

公开(公告)号：US07309892B2

公开(公告)日：2007-12-18

申请号：US11439152

申请日：2006-05-24

申请人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/94

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

摘要翻译： 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US07298662B2

公开(公告)日：2007-11-20

申请号：US11483649

申请日：2006-07-11

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。