公开(公告)号：US20060043494A1

公开(公告)日：2006-03-02

申请号：US11210666

申请日：2005-08-25

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。

公开(公告)号：US07005705B2

公开(公告)日：2006-02-28

申请号：US10261665

申请日：2002-10-02

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

公开(公告)号：US20050269637A1

公开(公告)日：2005-12-08

申请号：US11137586

申请日：2005-05-26

申请人： Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/105 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78615 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78609

摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

摘要翻译： 在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即， （隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。

公开(公告)号：US06798021B2

公开(公告)日：2004-09-28

申请号：US10291703

申请日：2002-11-12

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2900

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： By ion implantation process, a P-type impurity for element isolation is implanted at an impurity concentration (P1) into a silicon layer (3) defined between the bottom surface of an element isolation insulating film (5a) and the upper surface of a BOX layer (2). Resulting from this implantation, a P-type impurity is implanted at an impurity concentration (P2) into the silicon layer (3) under a gate oxide film (7a) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2). Under a capacitor dielectric film (7b) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2), the silicon layer (3) has an impurity concentration (P0) which is the initial concentration of itself.

摘要翻译： 通过离子注入工艺，将元素隔离的P型杂质以杂质浓度（P1）注入到限定在元件隔离绝缘膜（5a）的底表面和BOX的上表面之间的硅层（3）中 层（2）。 通过该注入，在栅极氧化膜（7a）的下方，在硅层（3）与硅层（3）的界面附近，以杂质浓度（P2）向硅层（3）注入P型杂质， BOX层（2）。 在电容电介质膜（7b）的下方，在硅层（3）和BOX层（2）之间的界面附近，硅层（3）的杂质浓度（P0）为本身的初始浓度 。

公开(公告)号：US06707105B2

公开(公告)日：2004-03-16

申请号：US09814116

申请日：2001-03-22

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L2701

CPC分类号： H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

公开(公告)号：US06479330B2

公开(公告)日：2002-11-12

申请号：US09922812

申请日：2001-08-07

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2100

CPC分类号： H01L29/402 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28238 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66772 ,  H01L29/78609

摘要： At an edge portion of an FS gate electrode (10) beneath a side wall oxide film (106), an FS gate oxide film (101) is thicker. Relative to a surface of a silicon substrate (SB) beneath the FS gate oxide film (101), other surface of the silicon substrate (SB) is retracted. Thus, a MOS transistor with field-shield isolation structure and a method for manufacturing the same can be provided with higher reliability of the gate oxide film.

公开(公告)号：US6091158A

公开(公告)日：2000-07-18

申请号：US990075

申请日：1997-12-12

申请人： Toshiaki Iwamatsu

发明人： Toshiaki Iwamatsu

摘要： A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

公开(公告)号：US08513058B2

公开(公告)日：2013-08-20

申请号：US13019686

申请日：2011-02-02

申请人： Toshiaki Iwamatsu ,  Yuichi Hirano

发明人： Toshiaki Iwamatsu ,  Yuichi Hirano

IPC分类号： H01L25/00 ,  H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

摘要： a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the first layer.

摘要翻译： 一种制造半导体器件的方法，其以层叠第一层和第二层的方式设置，以确保其TSV几乎为直线布置，包括：第一层制造步骤，包括制备基板，形成 在衬底的上表面上的输入/输出电路的晶体管，形成绝缘层以覆盖晶体管，并在绝缘层中形成TSV; 第二层制造步骤包括制备衬底的步骤，在衬底的上表面上形成逻辑电路的晶体管，形成绝缘层以覆盖晶体管，并在绝缘层中形成TSV; 将第一层和第二层的表面连接在与第一层和第二层的基板相对的一侧的连接步骤，以确保第一层的TSV和第二层的TSV几乎为直线 线; 以及去除第一层的基板的步骤。

公开(公告)号：US08350331B2

公开(公告)日：2013-01-08

申请号：US11627167

申请日：2007-01-25

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

摘要翻译： 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。

公开(公告)号：US08269288B2

公开(公告)日：2012-09-18

申请号：US12253563

申请日：2008-10-17

申请人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

发明人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

IPC分类号： H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。