公开(公告)号：US07839312B2

公开(公告)日：2010-11-23

申请号：US12439004

申请日：2007-10-11

Applicant: Toshihiro Tanaka ,  Keiichi Ishida

Inventor： Toshihiro Tanaka ,  Keiichi Ishida

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/126 ,  H04N19/13 ,  H04N19/149 ,  H04N19/15 ,  H04N19/194 ,  H04N19/436 ,  H04N19/46 ,  H04N19/70

Abstract: A coder has a binarizing circuit (130) for converting multivalued data into a binary symbol sequence, the multivalued data being generated from an input signal and having a plurality of contexts, an arithmetic code amount approximating circuit (200) for calculating a prediction code amount in the predetermined coding unit from the binary symbol sequence, and a coding circuit (102) for coding the input signal arithmetically on the basis of the prediction code amount. The arithmetic code amount approximating circuit (200) includes a selector (230) for dividing the binary symbol sequence into a plurality of groups based on the contexts, a plurality of code amount approximating circuits (211-214) for calculating, from the binary symbol sequence divided into a plurality of groups, the prediction code amount of the group based on at least the section range in arithmetic coding, and an adder (231) for adding the prediction code amounts from all code amount approximating circuits and outputting the prediction code amount in the specified coding unit.

Abstract translation: 编码器具有二值化电路（130），用于将多值数据转换为二进制符号序列，多值数据从输入信号产生并具有多个上下文，算术码量近似电路（200）用于计算预测代码量 在二进制符号序列的预定编码单元中，以及编码电路（102），用于根据预测码量对算术输入信号进行编码。 算术码量近似电路（200）包括：用于根据上下文将二进制符号序列划分为多个组的选择器（230），用于从二进制符号计算的多个码量近似电路（211-214） 序列划分为多个组，基于算术编码中的至少区间范围的组的预测编码量，以及用于从所有码量近似电路中相加预测码量的加法器（231），并输出预测码量 在指定的编码单位。

公开(公告)号：US07821824B2

公开(公告)日：2010-10-26

申请号：US12258964

申请日：2008-10-27

Applicant: Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

Inventor： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC: G11C16/04

CPC classification number: G11C16/349 ,  G11C16/06 ,  G11C16/3495

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

Abstract translation: 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US20100233684A1

公开(公告)日：2010-09-16

申请号：US12304559

申请日：2007-06-15

Applicant: Toshihiro Tanaka ,  Yusuke Nakamura ,  Aritoshi Iida ,  Kouichi Ozaki ,  Masatsugu Hori

Inventor： Toshihiro Tanaka ,  Yusuke Nakamura ,  Aritoshi Iida ,  Kouichi Ozaki ,  Masatsugu Hori

IPC: C12Q1/68 ,  C07H21/04

CPC classification number: G01N33/6893 ,  A61K31/7088 ,  C12Q1/6883 ,  C12Q2600/136 ,  C12Q2600/156 ,  C12Q2600/158 ,  C12Q2600/172 ,  G01N2500/00 ,  G01N2800/324

Abstract: It is an object of the present invention to provide a method for determining inflammatory diseases including myocardial infarction as a typical example, which involves identifying polymorphisms associated with myocardial infarction and using the gene polymorphisms, an oligonucleotide that can be used for the method, a kit for diagnosing inflammatory diseases, a therapeutic agent for inflammatory diseases, and the like. The present invention provides a method for determining an inflammatory disease, which comprises detecting at least one type of gene polymorphism existing in a proteasome subunit α type 6 gene.

Abstract translation: 本发明的目的是提供一种用于确定包括心肌梗塞在内的炎性疾病的方法，其中包括鉴定与心肌梗塞相关的多态性和使用基因多态性，可用于该方法的寡核苷酸，试剂盒 用于诊断炎性疾病，炎症性疾病的治疗剂等。 本发明提供一种测定炎性疾病的方法，其包括检测存在于蛋白酶体亚单位α6型基因中的至少一种基因多态性。

公开(公告)号：US20100038700A1

公开(公告)日：2010-02-18

申请号：US12580289

申请日：2009-10-16

Applicant: Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

Inventor： Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/792

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US07502257B2

公开(公告)日：2009-03-10

申请号：US11797164

申请日：2007-05-01

Applicant: Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: G11C11/34

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US07447959B2

公开(公告)日：2008-11-04

申请号：US11785537

申请日：2007-04-18

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC: G01R31/28 ,  G06K5/04

CPC classification number: G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract translation: 其中可以容易地与其他LSI并行设置用于确定其本身产生的脉冲的电压或宽度的控制信息的半导体集成电路（LSI），并且可以容易地校正设置信息。 从外部评估装置，将预期值的电压重叠地提供给具有CPU和闪速存储器的多个LSI。 每个LSI包含比较电路，其比较期望的电压值和本身产生的升压电压。 CPU参考比较结果并优化用于改变升压电压的数据寄存器中的控制数据。 CPU控制比较电路和数据寄存器，并且以自完成方式进行修整，从而以并行方式容易地对多个LSI进行修整，并且总的测试时间减少。

公开(公告)号：US20080220420A1

公开(公告)日：2008-09-11

申请号：US11667971

申请日：2005-11-18

Applicant: Yusuke Nakamura ,  Toshihiro Tanaka ,  Yozo Ohnishi ,  Nobuhiro Hanafusa ,  Koretsugu Ogata ,  Satoshi Yomota

Inventor： Yusuke Nakamura ,  Toshihiro Tanaka ,  Yozo Ohnishi ,  Nobuhiro Hanafusa ,  Koretsugu Ogata ,  Satoshi Yomota

IPC: C12Q1/68 ,  C12M1/00

CPC classification number: C12Q1/6806 ,  B01L3/5027 ,  B01L7/52 ,  B01L2200/16 ,  B01L2300/0816 ,  C12Q1/6858 ,  C12Q2561/101 ,  C12Q2537/143

Abstract: The object of the invention is to carry out typing for multiple SNP sites automatically from the stage of sample preparation. A mixture of sample (2) and PCR reaction solution (4) is subjected to PCR reaction according to a given temperature cycle. After the completion of PCR reaction, invader reagent (6) is added thereto. Subsequently, the reaction mixture having the invader reagent (6) added thereto is added to probe fixing part (8) of typing reaction zone to thereby effect reaction therebetween. Invader probes capable of emitting fluorescence in respective correspondence to multiple SNP sites are separately held on individual sites of the probe fixing part (8), so that the reaction mixture reacts with the invader probes and when SNPs corresponding to the invader probes exist, fluorescence is emitted.

Abstract translation: 本发明的目的是从样品制备阶段自动进行多个SNP位点的分型。 根据给定的温度循环对样品（2）和PCR反应溶液（4）的混合物进行PCR反应。 PCR反应完成后，加入入侵者试剂（6）。 随后，向其中添加有侵入试剂（6）的反应混合物加入到分型反应区的探针固定部分（8）中，从而在其间进行反应。 能够分别对应于多个SNP位点发射荧光的入侵者探针分别保存在探针固定部分（8）的各个位置，使得反应混合物与入侵者探针反应，并且当存在对应于入侵探针的SNP时，荧光是 发射。

公开(公告)号：US07414283B2

公开(公告)日：2008-08-19

申请号：US11415129

申请日：2006-05-02

Applicant: Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US20060209599A1

公开(公告)日：2006-09-21

申请号：US11438337

申请日：2006-05-23

Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

公开(公告)号：US07092296B2

公开(公告)日：2006-08-15

申请号：US11138290

申请日：2005-05-27

Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.