摘要:
A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要:
A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要:
A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.
摘要:
A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要:
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
摘要:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要:
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Sil-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Sil-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要:
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要:
In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.