公开(公告)号：US06940777B2

公开(公告)日：2005-09-06

申请号：US10694780

申请日：2003-10-29

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C29/02 ,  G11C7/00

CPC分类号： G11C11/16 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

摘要： An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

摘要翻译： 从电源节点向内部电路提供工作电流。 在测试模式中，电流从电源供应节点的电流由电流开关停止，外部可调试验电流被供给到电源节点。 测试电流根据内部电路中的漏电流的可接受值设定。 根据检测电源节点的电压降的电压比较电路的输出，评价内部电路的漏电电流是否不大于可接受值。

公开(公告)号：US06917540B2

公开(公告)日：2005-07-12

申请号：US10396481

申请日：2003-03-26

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C16/06 ,  G11C11/15 ,  G11C29/04 ,  G11C29/12

CPC分类号： G11C11/16 ,  G11C11/15 ,  G11C11/5607

摘要： Each of program cell and memory cells includes a magnetic storage portion of the same configuration. The program cell further includes a state change portion. That is, the program cell has the same structure as the memory cell, except that the state change portion is additionally provided thereto. As such, the program cell can be provided efficiently, as it can be designed the same as the memory cell in terms of the magnetic storage portion and others. The state change portion makes a transition to a fixed state based on an electrical change. Thus, the state change portion prevents program information from being rewritten by a magnetic noise or the like, and ensures stable storage of the program information.

公开(公告)号：US06901025B2

公开(公告)日：2005-05-31

申请号：US10461683

申请日：2003-06-16

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G06F12/00 ,  G06F13/00 ,  G11C5/00 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/16 ,  G11C29/02 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C29/022 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/1096 ,  G11C11/16 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2245

摘要： In a read operation, for example, 32 sense amplifiers read 32 pieces of data in a group. After that, the read data is outputted on a 4-bit unit basis. A memory cell array operates at a low frequency which is ⅛ of an actual data output frequency. On the other hand, in a write operation, data is transferred from the outside to a semiconductor memory device bit by bit every cycle. Consequently, by providing a number of latches of a pipeline in a write access path, the writing operation is enabled even at a high frequency. Specifically, at the time of reading, a memory array operates at a low frequency which is ⅛ of a data output frequency. At the time of writing, data is written every clock.

摘要翻译： 在读取操作中，例如，32个读出放大器读取一组中的32个数据。 之后，读取的数据以4位单位输出。 存储单元阵列在实际数据输出频率的1/8的低频下工作。 另一方面，在写入操作中，每个周期将数据从外部传送到半导体存储器件。 因此，通过在写访问路径中提供多个管道锁存器，甚至在高频率下也能够进行写入操作。 具体地，在读取时，存储器阵列以低于数据输出频率的1/8的低频运行。 在写入时，每个时钟写入数据。

公开(公告)号：US06879513B2

公开(公告)日：2005-04-12

申请号：US10396414

申请日：2003-03-26

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  G11C11/00

CPC分类号： G11C11/15

摘要： A current drive circuit operates receiving higher voltage than in a waiting mode at source terminal of a P-channel first driver transistor, when supplying a current to a node connected to a load circuit. In accordance with the rising source potential of the first driver transistor, the gate potential output to the first driver transistor by a gate potential control circuit rises. When the first and second driver transistors are off, a precharge circuit configured with a P-channel MOS transistor precharges the node to a prescribed potential. As a result, the current drive circuit is provided with increased reliability of the gate insulating films of the driver transistors without decreasing the driving current.

摘要翻译： 当向连接到负载电路的节点提供电流时，电流驱动电路操作接收比在P沟道第一驱动器晶体管的源极端处的等待模式更高的电压。 根据第一驱动晶体管的源极电位上升，由栅极电位控制电路向第一驱动晶体管输出的栅极电位上升。 当第一和第二驱动器晶体管截止时，配置有P沟道MOS晶体管的预充电电路将节点预充电到规定的电位。 结果，在不降低驱动电流的情况下，电流驱动电路具有提高驱动晶体管的栅极绝缘膜的可靠性。

公开(公告)号：US06873561B2

公开(公告)日：2005-03-29

申请号：US10409120

申请日：2003-04-09

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C7/00

CPC分类号： G11C11/15

摘要： In a resistance value variable memory, substrate voltages and/or substrate biases of a digit line drive circuit, a word line drive circuit and a bit line drive circuit for a memory cell array are changed in accordance with an operation mode. A driving power on signal lines connected to memory cells can be increased, and a leakage current during standby can be reduced without increasing a circuit layout area.

摘要翻译： 在电阻值可变存储器中，根据操作模式改变数字线驱动电路，字线驱动电路和用于存储单元阵列的位线驱动电路的衬底电压和/或衬底偏置。 可以增加连接到存储单元的信号线的驱动电源，并且可以在不增加电路布局面积的情况下降低待机期间的漏电流。

公开(公告)号：US06868031B2

公开(公告)日：2005-03-15

申请号：US10456530

申请日：2003-06-09

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C5/14 ,  G11C8/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C11/16 ,  G11C5/147

摘要： A memory block is divided into block units for which parallel data write is performed. Current supply sections capable of supplying a power supply voltage and a ground voltage are provided for block units, independently of one another. With this configuration, in each block unit, writing of data to a selected memory cell is performed by a data write current from the independent current supply section connected to the power supply voltage and the ground voltage. That is, wiring lengths of power supply lines for supplying the power supply voltage and the ground voltage can be shortened. It is therefore possible to suppress a wiring resistance of the power supply line and to supply a desired data write current.

摘要翻译： 存储器块被划分为执行并行数据写入的块单元。 为块单元提供能够提供电源电压和接地电压的电流供应部分彼此独立地设置。 利用这种配置，在每个块单元中，通过来自连接到电源电压和接地电压的独立电流供应部分的数据写入电流来执行将数据写入所选择的存储器单元。 也就是说，可以缩短用于提供电源电压和接地电压的电源线的布线长度。 因此，可以抑制电源线的布线电阻并提供期望的数据写入电流。

公开(公告)号：US06868029B2

公开(公告)日：2005-03-15

申请号：US10607259

申请日：2003-06-27

申请人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

发明人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

IPC分类号： G11C11/403 ,  G06F1/26 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  H01L27/148 ,  H03K19/00 ,  H03K19/096

CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

摘要翻译： 逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。 在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。 逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

公开(公告)号：US06856550B2

公开(公告)日：2005-02-15

申请号：US10298666

申请日：2002-11-19

申请人： Hiroshi Kato ,  Yasuhiko Taito ,  Tsukasa Ooishi ,  Jun Ohtani

发明人： Hiroshi Kato ,  Yasuhiko Taito ,  Tsukasa Ooishi ,  Jun Ohtani

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3454 ,  G11C2211/5634

摘要： At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

摘要翻译： 在将数据写入存储块中的特定存储单元的操作时，半导体存储器件施加预定周期的写入电压，然后通过使用读出放大器电路和比较器执行验证操作。 当作为对存储单元的写入不足的验证操作的结果发现，通过存储器控制电路的指令再次执行写入操作。 此时，存储器控制电路调整写入电压。

公开(公告)号：US06842366B2

公开(公告)日：2005-01-11

申请号：US10383570

申请日：2003-03-10

申请人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/14

CPC分类号： G11C11/15 ,  G11C11/1673

摘要： In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

摘要翻译： 在一个数据读取操作中，执行用于将预定数据写入磁场之前和之后的存储数据读取的数据分别施加到所选择的存储单元，并且根据与 数据读取操作在应用预定数据写入磁场之前和之后。 另外，数据写入磁场的应用前后的数据读取操作是使用读修改写进行的。 从而可以避免在形成数据读取路径的各个电路中由制造不规则引起的偏移等的影响，从而精确地提高数据读取操作的效率并执行高速数据读取操作。

公开(公告)号：US06829173B2

公开(公告)日：2004-12-07

申请号：US10305000

申请日：2002-11-27

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C1604

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26

摘要： In storing multiple data into a storage area of a first nonvolatile memory cell and into a storage area of a second nonvolatile memory cell in a memory cell array, a first control circuit turns on a switch circuit to supply a predetermined write potential to a bit line, and a second control circuit turns on two switch circuits to supply a source potential to each of two bit lines according to the combination of multiple data to be stored in each memory cell.

摘要翻译： 在将多个数据存储到存储单元阵列中的第一非易失性存储单元的存储区域和第二非易失性存储单元的存储区域中时，第一控制电路接通开关电路以向位线提供预定的写入电位 并且第二控制电路根据要存储在每个存储单元中的多个数据的组合，打开两个开关电路以向两个位线中的每一个提供源极电位。