公开(公告)号：US08060252B2

公开(公告)日：2011-11-15

申请号：US11998858

申请日：2007-11-30

申请人： Chris Gage ,  Damon Genetti

发明人： Chris Gage ,  Damon Genetti

IPC分类号： G05B19/418

CPC分类号： H01L21/68 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67742

摘要： Methods correcting wafer position error are provided. The methods involve measuring wafer position error on a robot, e.g. a dual side-by-side end effector robot, during transfer to an intermediate station. This measurement data is then used by a second robot to perform wafer pick moves from the intermediate station with corrections to center the wafer. Wafer position correction may be performed at only one location during the transfer process. Also provided are systems and apparatuses for transferring wafers using an intermediate station.

摘要翻译： 提供校正晶片位置误差的方法。 该方法涉及测量机器人上的晶片位置误差，例如。 双向并排端部执行器机器人，在传送到中间站时。 该测量数据然后被第二机器人用于执行从中间站的晶片拾取移动，其具有校正以使晶片居中。 晶片位置校正可以在传送过程中仅在一个位置进行。 还提供了使用中间站传送晶片的系统和装置。

公开(公告)号：US08058179B1

公开(公告)日：2011-11-15

申请号：US12343102

申请日：2008-12-23

申请人： Nerissa Draeger ,  Harald te Nijenhuis ,  Henner Meinhold ,  Bart van Schravendijk ,  Lakshmi Nittala

发明人： Nerissa Draeger ,  Harald te Nijenhuis ,  Henner Meinhold ,  Bart van Schravendijk ,  Lakshmi Nittala

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/76837

摘要： Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the reaction is partially “reset.” A higher overall etch rate is achieved by a multiple exposure with pump down ALR process.

摘要翻译： 实现更高的总体蚀刻速率和原子层去除（ALR）的吞吐量。 反应是一种自限制过程，因此限制了每个循环可蚀刻的材料的总量。 通过在反应操作之间泵送工艺站，反应部分地“重新设置”。通过多次曝光通过泵浦ALR工艺实现更高的总体蚀刻速率。

公开(公告)号：US08053372B1

公开(公告)日：2011-11-08

申请号：US11520497

申请日：2006-09-12

申请人： Frank Greer ,  Karl Leeser

发明人： Frank Greer ,  Karl Leeser

IPC分类号： H01L21/36 ,  B01J19/08 ,  C23C16/453

CPC分类号： C23C16/45538 ,  C23C16/45523 ,  H01J37/32082 ,  H01J37/32137

摘要： The present invention relates to an enhanced cyclic deposition process suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. The deposition enhancement is derived from ions generated in a plasma. The techniques described reduce the time required for plasma stabilization, thereby reducing deposition time and improving efficiency.

摘要翻译： 本发明涉及一种适用于沉积阻挡层，粘附层，种子层，低介电常数（低k）膜，高介电常数（高k）膜）和其它导电半导体膜的增强循环沉积工艺 ，和非导电膜。 沉积增强源自在等离子体中产生的离子。 所描述的技术减少了等离子体稳定化所需的时间，从而减少了沉积时间并提高了效率。

公开(公告)号：US08048280B2

公开(公告)日：2011-11-01

申请号：US11228712

申请日：2005-09-16

申请人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

发明人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

IPC分类号： C25D5/18 ,  C25D7/12 ,  H01L21/768

CPC分类号： C25D3/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

摘要翻译： 描述了几种用于减少或减轻在电镀微观凹陷特征的内部区域中的接缝和/或空隙的形成的技术。 阴极极化用于减轻将电镀有种子层的基板引入电镀溶液中的有害影响。 还描述了扩散控制的电镀技术，以提供沟槽和通孔的自下而上的填充，从而避免由此侧壁一起生长以产生接缝/空隙。 还描述了初步电镀步骤，在特征的内表面上镀覆导电薄膜，导致特征底部具有足够的导电性，便于自底向上填充。

公开(公告)号：US08043958B1

公开(公告)日：2011-10-25

申请号：US12875857

申请日：2010-09-03

申请人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

发明人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

IPC分类号： H01L21/302 ,  H01L21/461 ,  B24B7/00

CPC分类号： H01L21/7684 ,  C23C18/1607 ,  C23C18/1882 ,  C25D5/02 ,  C25D7/123 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76883 ,  Y10S414/135

摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。

公开(公告)号：US08043484B1

公开(公告)日：2011-10-25

申请号：US11830777

申请日：2007-07-30

申请人： Robert Rozbicki

发明人： Robert Rozbicki

IPC分类号： C23C14/00 ,  C23C14/32 ,  H01L21/76 ,  H01L21/00

CPC分类号： H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865

摘要： Conductive or barrier material is deposited on a semiconductor substrate having recessed features by a method that has at least two operations. The first operation involves depositing a layer of the material on at least a portion of the field regions of the wafer. The second operation involves resputtering at least the layer residing on the field region of the wafer under high pressure. If the pressure is sufficiently high, momentum transfer reflection of the resputtered material will take place, such that at least some of the resputtered material is placed in the recessed features of the wafer. This approach can, among other advantages, offer improved step coverage and better utilization of the material.

摘要翻译： 通过具有至少两个操作的方法将导电或阻挡材料沉积在具有凹陷特征的半导体衬底上。 第一操作包括在晶片的场区域的至少一部分上沉积材料层。 第二操作涉及至少在高压下溅射位于晶片的场区域上的层。 如果压力足够高，则会发生被溅射的材料的动量传递反射，使得至少一些被重排的材料被放置在晶片的凹陷特征中。 除了其它优点之外，这种方法可以提供改进的步骤覆盖和更好地利用材料。

公开(公告)号：US08030777B1

公开(公告)日：2011-10-04

申请号：US11671161

申请日：2007-02-05

申请人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

发明人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

IPC分类号： H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886

摘要： Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

摘要翻译： 在制造电子部件的方法和根据这些方法制造的电子部件的过程中保护暴露的金属镶嵌互连表面的方法。 具有暴露的金属表面的镶嵌区域的集成电路结构被提供到封闭处理室中，由此第一反应物与暴露的金属表面接触以将金属层的顶部部分转变成保护性自对准缓冲层。 使第一反应物与该金属层的金属原子反应的分子在该金属层内完全形成保护性自对准缓冲层。 或者，将表面活性反应物分子吸附到暴露的金属表面上形成保护性自对准缓冲层。 可以将第二反应物与保护性自对准缓冲层接触以在保护性自对准缓冲层上直接形成自对准电介质盖层。

公开(公告)号：US20110217465A1

公开(公告)日：2011-09-08

申请号：US13039641

申请日：2011-03-03

申请人： Karl Leeser ,  Yajie Liu

发明人： Karl Leeser ,  Yajie Liu

IPC分类号： C23C16/00

CPC分类号： C23C16/00

摘要： A shielding system for a physical vapor deposition (PVD) chamber is disclosed. The PVD chamber includes a pedestal supporting a substrate. The shielding system includes a first annular portion and a second annular portion of a pedestal shield. The first annular portion is attached the pedestal at a first location. The first annular portion is located at or below a plane including the substrate. The second annular portion is attached to the pedestal at a second location that is below the first location. The first annular portion is spaced a predetermined distance from the second annular portion and is electrically isolated from the second annular portion.

摘要翻译： 公开了一种用于物理气相沉积（PVD）室的屏蔽系统。 PVD室包括支撑衬底的基座。 屏蔽系统包括基座屏蔽件的第一环形部分和第二环形部分。 第一环形部分在第一位置附接基座。 第一环形部分位于包括基底的平面上或下方。 第二环形部分在位于第一位置下方的第二位置附接到基座。 第一环形部分与第二环形部分隔开预定的距离并且与第二环形部分电隔离。

公开(公告)号：US07993457B1

公开(公告)日：2011-08-09

申请号：US11626328

申请日：2007-01-23

申请人： Peter Krotov ,  Colin F. Smith

发明人： Peter Krotov ,  Colin F. Smith

IPC分类号： C23C16/458 ,  C23F1/00 ,  H01L21/306 ,  C23C16/22 ,  C23C16/06

CPC分类号： C23C16/45517 ,  C23C16/45544

摘要： An apparatus and method for depositing film on a substrate includes a plurality of conduits that allow by-product and reactant gases to flow past the edge of a substrate. The apparatus and process of the present invention has several advantages for enhanced chamber performance, particularly for micro-volume chambers using pulsed deposition layer processes.

摘要翻译： 用于在衬底上沉积膜的设备和方法包括允许副产物和反应物气体流过衬底边缘的多个管道。 本发明的装置和方法对于提高室性能具有几个优点，特别是对于使用脉冲沉积层工艺的微体积室。

公开(公告)号：US07967969B2

公开(公告)日：2011-06-28

申请号：US12578310

申请日：2009-10-13

申请人： Steven T. Mayer ,  Jonathan D. Reid

发明人： Steven T. Mayer ,  Jonathan D. Reid

IPC分类号： C25D5/00 ,  C25D7/12 ,  C25D21/12

CPC分类号： C25D17/12 ,  C25D7/123 ,  C25D17/001 ,  C25D17/008 ,  H01L21/2885 ,  Y10S204/07

摘要： A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.

摘要翻译： 将基本上均匀的金属层电镀在其上具有种子层的工件上。 这是通过使用“高电阻离子电流源”来实现的，其通过将高电阻膜（例如，微孔陶瓷或微波玻璃元件）放置在靠近晶片来解决端子问题，从而消除系统的电阻。 因此，膜近似于恒定电流源。 通过保持晶片靠近膜表面，从膜顶部到表面的离子电阻远小于对晶片边缘的离子路径电阻，基本上补偿薄金属膜中的薄层电阻并引导附加电流 在晶片的中心和中间。