公开(公告)号：US20150092493A1

公开(公告)日：2015-04-02

申请号：US14563243

申请日：2014-12-08

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Alexander Kwok-Tung Mak ,  Chris Avila ,  Gautam Dusija ,  Man Mui

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/14

CPC分类号： G11C16/107 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

摘要： A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

摘要翻译： 一种3D NAND堆叠非易失性存储器件，包括：包括多个非易失性存储元件的串，所述串包括通道并垂直延伸穿过所述3D堆叠非易失性存储器件的层，并且所述多个存储元件 基于组分配被细分为不同的组，每组不同组包括多个存储元件中的多个相邻存储元件; 以及控制电路，与控制电路串联连接，以执行伪块操作模式。

公开(公告)号：US08977808B2

公开(公告)日：2015-03-10

申请号：US14304420

申请日：2014-06-13

申请人： Micron Technology, Inc.

发明人： Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Mustafa N. Kaynak ,  Zhenlei Shen

IPC分类号： G06F12/06 ,  G11C16/00 ,  G11C16/10 ,  G11C14/00 ,  G06F12/02 ,  G11C16/04 ,  G11C13/00 ,  G11C11/56

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F12/06 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/0002 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  H03M7/14

摘要： The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.

摘要翻译： 本公开包括用于在程序状态和数据模式之间进行映射的方法和装置。 一种方法包括：对一组G存储器单元进行编程，使得该组的各个程序状态的组合映射到与接收到的N单位数据模式对应的星座点，该组用于存储每个存储单元的N / G个数据单元 ; 其中所述星座点是与将所述存储器单元组的各个程序状态组合映射到N个单位数据模式相关联的星座的多个星座点中的一个; 并且其中所述星座包括第一映射外壳和第二映射外壳，所述星座点对应于相应的第一和第二映射外壳，至少部分地基于等于G的等级的多项式表达式确定。

公开(公告)号：US20150039813A1

公开(公告)日：2015-02-05

申请号：US14445047

申请日：2014-07-28

申请人： Greenliant LLC

发明人： Chuan-Ding Arthur Hsu ,  Siamak Arya ,  Yung-Chin Chen ,  Lei Zhang ,  Dongsheng Xing

IPC分类号： G11C16/10

CPC分类号： G11C16/107 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0688 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A system and method for a solid state drive comprising a system controller and one or more extender devices coupled to the system controller is disclosed, where each extender device is coupled to a plurality of NAND storage devices and each NAND storage device comprising a plurality of NAND flash memory cells.

摘要翻译： 公开了一种用于固态驱动器的系统和方法，其包括耦合到系统控制器的系统控制器和一个或多个扩展器设备，其中每个扩展器设备耦合到多个NAND存储设备，并且每个NAND存储设备包括多个NAND 闪存单元。

公开(公告)号：US08923054B1

公开(公告)日：2014-12-30

申请号：US14152848

申请日：2014-01-10

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Alexander Kwog-Tung Mak ,  Chris Avila ,  Gautam Dusija ,  Man Mui

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC分类号： G11C16/107 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

摘要： A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

公开(公告)号：US20140369122A1

公开(公告)日：2014-12-18

申请号：US14152848

申请日：2014-01-10

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Alexander Kwok-Tung Mak ,  Chris Avila ,  Gautam Dusija ,  Man Mui

IPC分类号： G11C16/10 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/107 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

摘要： A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

摘要翻译： 一种3D NAND堆叠非易失性存储器件，包括：包括多个非易失性存储元件的串，所述串包括通道并垂直延伸穿过所述3D堆叠非易失性存储器件的层，并且所述多个存储元件 基于组分配被细分为不同的组，每组不同组包括多个存储元件中的多个相邻存储元件; 以及控制电路，与控制电路串联连接，以执行伪块操作模式。

公开(公告)号：US20140362645A1

公开(公告)日：2014-12-11

申请号：US14279405

申请日：2014-05-16

申请人： SanDisk Technologies Inc.

发明人： Yingda Dong ,  Wendy Ou ,  Man L. Mui ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/107 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3472 ,  H01L27/11582 ,  H01L29/7926

摘要： A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

摘要翻译： 提供了用于补偿存储器孔直径的变化的3D堆叠的非易失性存储器件的结构和制造工艺。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，字线层在堆叠的底部较厚，并且可以从堆叠的底部到顶部逐渐增加。 结果，存储器单元的控制栅极的长度在堆叠的底部更大。 控制栅极和电荷捕获层之间的电容与控制栅极的长度成比例地增加。 在编程期间，对于这些存储单元实现了较窄的阈值电压（Vth）分布。 可以将Vth分布放置得更靠近在一起并降档以允许在随后的感测操作中降低读通过电压，从而减少读取干扰。

公开(公告)号：US20140362642A1

公开(公告)日：2014-12-11

申请号：US13910388

申请日：2013-06-05

申请人： SanDisk Technologies Inc.

发明人： Yingda Dong ,  Wendy Ou ,  Man L Mui ,  Masaaki Higashitani

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/107 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3472 ,  H01L27/11582 ,  H01L29/7926

摘要： A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

公开(公告)号：US20140362641A1

公开(公告)日：2014-12-11

申请号：US13910377

申请日：2013-06-05

申请人： SanDisk Technologies Inc.

发明人： Yingda Dong ,  Wendy Ou ,  Man L. Mui ,  Masaaki Higashitani

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/107 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/1157 ,  H01L27/11582

摘要： Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.

摘要翻译： 提供了通过补偿存储器孔直径的变化来编程和读取3D堆叠的非易失性存储器件中的存储器单元的技术。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，在较低字线层处的存储器单元的编程被修改。 在一种方法中，编程期间一个或多个数据状态的阈值电压（Vth）分布变窄，从而可以在随后的感测操作中使用较低的读通过电压。 在读通道电压和最高数据状态的上尾之间保持足够的间隔。 Vth分布也可以降档。 在另一种方法中，读通道电压不降低，但是最低编程状态被升高以提供与擦除状态的上尾的间隔。

公开(公告)号：US20140351487A1

公开(公告)日：2014-11-27

申请号：US14217538

申请日：2014-03-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： TAE-YOUNG KIM

IPC分类号： G11C16/10

CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/344 ,  G11C16/3459

摘要： A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells.

摘要翻译： 一种对非易失性存储器件进行重新编程的方法，包括根据连接到位线的页缓冲器的第一和第二锁存器的逻辑值设置所选存储器单元的位线，向所选存储单元提供编程脉冲，执行程序 使用第一和第二锁存器对所选择的存储器单元进行验证操作，并且根据程序验证操作的结果对选择的存储器单元执行预测程序操作。 在预测编程操作中，所选择的存储器单元的位线根据对应于所选择的每个存储器单元的页缓冲器的第三锁存器的逻辑值进行设置。

公开(公告)号：US20140250280A1

公开(公告)日：2014-09-04

申请号：US14283117

申请日：2014-05-20

申请人： Micron Technology, Inc.

发明人： Federico Pio

IPC分类号： G11C14/00

CPC分类号： G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

摘要翻译： 提供了一种访问存储器件的方法。 该方法包括在第一编程操作中在存储器件的多个单元中编程数据。 第一编程操作使用包括代表用于所述编程的至少一个第一阈值电压值的至少一个第一参数的第一存储器指令。 该方法还包括在第二编程操作中对多个单元中的数据的至少一部分进行重新编程。 第二编程操作使用包括表示用于所述重新编程的至少一个第二阈值电压值的至少一个第二参数的第二存储器指令，其中所述重新编程提供对所述数据的该部分的位操作。