公开(公告)号：US20240234352A9

公开(公告)日：2024-07-11

申请号：US18450435

申请日：2023-08-16

申请人： ADVANTEST CORPORATION ,  Tokyo Institute of Technology

发明人： Shinji SUGATANI ,  Takayuki OHBA ,  Norio CHUJO ,  Koji SAKUI ,  Tadashi FUKUDA

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC分类号： H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

公开(公告)号：US20240234345A1

公开(公告)日：2024-07-11

申请号：US18537160

申请日：2023-12-12

申请人： UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED

发明人： Swarup BHUNIA ,  Peyman Dehghanzadeh

IPC分类号： H01L23/58 ,  H01L23/48 ,  H01L25/18 ,  H02J7/00 ,  H03F3/45

CPC分类号： H01L23/58 ,  H01L25/18 ,  H03F3/45475 ,  H01L23/481 ,  H02J7/0063

摘要： A three-dimensional integrated circuit is provided. In various embodiments, the three-dimensional integrated circuit includes a first electronic module disposed on a substrate of the three-dimensional integrated circuit and a first battery disposed on the first electronic module and electronically coupled to the first electronic module. The first battery may be configured to provide power to the first electronic module. The three-dimensional integrated circuit includes a second electronic module disposed on the first battery, and a second battery disposed on the second electronic module and electronically coupled to the second electronic module. The second battery may be configured to provide power to the second electronic module.

公开(公告)号：US20240234294A1

公开(公告)日：2024-07-11

申请号：US18393092

申请日：2023-12-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jisu Yu ,  Jungho Do ,  Sungyup Jung

IPC分类号： H01L23/50 ,  H01L23/48 ,  H01L23/538 ,  H01L25/16

CPC分类号： H01L23/50 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/16

摘要： An integrated circuit includes: a plurality of first power rails extending in a first horizontal direction and configured to provide a first power supply voltage that is applied thereto; a plurality of second power rails extending in the first horizontal direction and configured to provide a second power supply voltage that is applied thereto; and a power line in a switch cell area and extending in the first horizontal direction the power line being configured to provide a global power supply voltage that is applied thereto, wherein the plurality of first power rails and the plurality of second power rails are alternately arranged in a second horizontal direction vertical to the first horizontal direction, wherein the plurality of first power rails, the plurality of second power rails, and the power line form a front-side pattern on a same layer, and wherein the power line is provided between two second power rails adjacent to each other in the first horizontal direction, among the plurality of second power rails.

公开(公告)号：US20240234276A9

公开(公告)日：2024-07-11

申请号：US18374792

申请日：2023-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chiwan SONG ,  Hyunna BAE ,  Joohyung LEE ,  Jaewook JUNG ,  Seungmin BAEK ,  Junghyun CHO

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

CPC分类号： H01L23/49822 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/08 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/08225 ,  H01L2224/48145 ,  H01L2224/48227

摘要： A semiconductor package includes: a chip-via composite substrate including a substrate, a semiconductor chip, and a plurality of through vias, wherein the substrate has a first surface and a second surface opposite to the first surface and includes a first region and a second region around the first region, wherein the semiconductor chip is provided in the first region and has chip pads and circuit patterns that are electrically connected to the chip pads, and wherein the plurality of through vias is provided in the second region and penetrate the substrate; a first redistribution wiring layer provided on the first surface of the substrate and having first redistribution wirings that are electrically connected to the chip pads and the through vias; and a second redistribution wiring layer provided on the second surface of the substrate and having second redistribution wirings that are electrically connected to the through vias.

公开(公告)号：US20240234255A1

公开(公告)日：2024-07-11

申请号：US18615528

申请日：2024-03-25

申请人： SK hynix Inc.

发明人： Ho Young SON ,  Sung Kyu KIM ,  Mi Seon LEE

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513

摘要： A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

公开(公告)号：US20240234252A1

公开(公告)日：2024-07-11

申请号：US18380325

申请日：2023-10-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： SHING-YIH SHIH

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76831 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541

摘要： The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.

公开(公告)号：US12033981B2

公开(公告)日：2024-07-09

申请号：US17123350

申请日：2020-12-16

申请人： International Business Machines Corporation

发明人： David Abraham ,  Oliver Dial ,  John Michael Cotte ,  Kevin Shawn Petrarca

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L23/06 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/06 ,  H01L23/481 ,  H01L25/50 ,  H01L2225/06513

摘要： A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

公开(公告)号：US12033980B2

公开(公告)日：2024-07-09

申请号：US16871443

申请日：2020-05-11

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Michel Koopmans

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2224/141 ,  H01L2924/00012

摘要： Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US20240224488A1

公开(公告)日：2024-07-04

申请号：US18089865

申请日：2022-12-28

申请人： Intel Corporation

发明人： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC分类号： H10B10/00 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00

CPC分类号： H10B10/125 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/056

摘要： Structures having two-level memory are described. In an example, an integrated circuit structure includes an SRAM layer including transistors. A DRAM layer is vertically spaced apart from the transistors of the SRAM layer. A metallization structure is between the transistors of the SRAM layer and the DRAM layer.

公开(公告)号：US20240222450A1

公开(公告)日：2024-07-04

申请号：US18221479

申请日：2023-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Eui Bok LEE ,  Moon Kyun SONG

IPC分类号： H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a fin-shaped pattern, a field insulating film covering a sidewall of the fin-shaped pattern, a source/drain pattern disposed on an upper surface of the fin-shaped pattern, a source/drain etch stop film extending along an upper surface of the field insulating film and a sidewall of the source/drain pattern, a source/drain contact connected to the source/drain pattern, a buried conductive pattern penetrating through a substrate and connected to the source/drain contact, a portion of the buried conductive pattern being disposed within the field insulating film, and a rear wiring line connected to the buried conductive pattern. The field insulating film includes a first field filling film and a first field stop film. The first field stop film is disposed between the first field filling film and the substrate. The first field stop film includes a material having etch selectivity with respect to the first field filling film.