公开(公告)号：US09318336B2

公开(公告)日：2016-04-19

申请号：US13326767

申请日：2011-12-15

申请人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

公开(公告)号：US09207106B2

公开(公告)日：2015-12-08

申请号：US14018548

申请日：2013-09-05

申请人： International Business Machines Corporation

发明人： Laura Wynter ,  Ioannis Kamarianakis

IPC分类号： G06G7/76 ,  G06F17/18 ,  G01D18/00 ,  G01D3/10

CPC分类号： G01D18/002 ,  G01D3/10

摘要： Systems and methods for incident detection are provided. A system for incident detection includes a network including at least one detector for detecting events in the network, a detection module capable of processing data from the at least one detector, and a calibration module capable of calibrating a plurality of bands for the incident detection based on a plurality of decision variables, wherein the plurality of bands define thresholds that are time-varying for all measurement locations in the network, and the thresholds are estimated using nonparametric quantile regression.

公开(公告)号：US09202863B2

公开(公告)日：2015-12-01

申请号：US13826936

申请日：2013-03-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Daniel C. Edelstein ,  Elbert E. Huang ,  Robert D. Miller

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/528 ,  G03F7/00 ,  G03F7/2022 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure which has at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

摘要翻译： 在金属互连件的表面上设置有用于形成绝缘体材料中的气隙的自对准抗蚀剂层的结构及其制造方法。 非平版印刷方法包括在具有形成在绝缘体材料中的至少一个金属互连的结构上涂覆抗蚀剂。 该方法还包括将抗蚀剂覆盖曝光到能量并显影抗蚀剂以暴露绝缘体材料的表面，同时保护金属互连。 该方法还包括通过蚀刻工艺在绝缘体材料中形成气隙，同时金属互连保持被抗蚀剂保护。

公开(公告)号：US09190118B2

公开(公告)日：2015-11-17

申请号：US13968845

申请日：2013-08-16

申请人： International Business Machines Corporation

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L27/06

CPC分类号： G11C5/063 ,  G11C5/025 ,  H01L27/0688

摘要： Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.

摘要翻译： 提供了多维存储器架构，其具有能够在多个维度上实现不同访问模式的访问布线结构。 此外，提供具有多维高速缓存存储器结构的三维多处理器系统，其具有允许多个维度中的不同访问模式的访问布线结构。

公开(公告)号：US09185807B2

公开(公告)日：2015-11-10

申请号：US14708755

申请日：2015-05-11

申请人： International Business Machines Corporation

发明人： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, Jr. ,  David B. Stone

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H05K1/183 ,  H05K1/0231 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K2201/09645 ,  H05K2201/10015 ,  H05K2201/10507 ,  Y02P70/611 ,  Y10T29/49135

摘要： Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.

摘要翻译： 各种实施例包括具有离轴孔内电容器的集成电路结构。 在一些实施例中，集成电路（IC）结构包括：具有上表面的基底层; 至少部分地包含在所述衬底层内并与垂直于所述衬底层的上表面的短轴对准的IC芯片; 所述基板层中的孔，所述孔与所述IC芯片物理分离; 以及孔中的电容器，并且至少部分地包含在所述衬底层内，所述电容器与所述IC芯片物理隔离，其中所述电容器与垂直于所述衬底层的上表面的轴线对准，并且偏离所述衬底层的短轴 IC芯片。

公开(公告)号：US09182686B2

公开(公告)日：2015-11-10

申请号：US13916939

申请日：2013-06-13

申请人： International Business Machines Corporation

发明人： Dario L. Goldfarb

IPC分类号： C25B9/00 ,  C25B9/18 ,  C25D17/00 ,  C25D17/08 ,  C25C7/02 ,  C25C3/10 ,  C25F7/00 ,  G03F7/20 ,  C25D11/32 ,  C25D17/06 ,  C25D11/00

CPC分类号： G03F7/70983 ,  C25D11/005 ,  C25D11/32 ,  C25D17/008 ,  C25D17/06 ,  G03F1/62

摘要： Spacers arranged on opposite sides of an article to be processed into an EUV pellicle support the article. Plates on opposite ends of the spacer-article combination include respective electrodes. The plates, article, and spacers can be held together with a vacuum retention system. A center hole of each spacer forms a chamber with surfaces engaged by the spacer. A fluid entry extending from an outer surface of each spacer to its center hole allows delivery of fluid to each chamber. Additional spacers can be used to support additional articles. Additional plates and electrodes can also be used.

摘要翻译： 安置在要加工成EUV防护薄膜的物品的相对两侧的隔板支撑该物品。 间隔物组合的相对端的板包括各自的电极。 板，物品和间隔物可以用真空保持系统保持在一起。 每个间隔件的中心孔形成具有由间隔件接合的表面的室。 从每个间隔件的外表面延伸到其中心孔的流体入口允许将流体输送到每个室。 可以使用附加的间隔物来支撑附加的物品。 还可以使用附加的板和电极。

公开(公告)号：US09178827B2

公开(公告)日：2015-11-03

申请号：US13958841

申请日：2013-08-05

申请人： International Business Machines Corporation

发明人： Marc A. Kaplan ,  Anna S. Povzner

IPC分类号： H04L1/00 ,  H04L12/819

CPC分类号： H04L47/215

摘要： Aspects of the invention are provided for rate control and management of service requests. A token bucket is employed in conjunction with a capacity sharing scheme to manage processing of service requests. Each token represents the capacity reserved for a particular source of requests. Excess tokens may be shed, with the excess tokens representing available excess capacity. Similarly, a projected time at which the service request(s) may be released may be computed in the event the bucket does not contain the required quantity of tokens to process the request.

摘要翻译： 本发明的方面被提供用于速率控制和服务请求的管理。 令牌桶与容量共享方案结合使用以管理服务请求的处理。 每个令牌表示为特定的请求源保留的容量。 过多的令牌可能会流失，多余的令牌表示可用的过剩容量。 类似地，可以在桶不包含处理请求的所需数量的令牌的情况下计算可以释放服务请求的预计时间。

公开(公告)号：US09176849B2

公开(公告)日：2015-11-03

申请号：US13864599

申请日：2013-04-17

申请人： GlobalFoundries U.S. 2 LLC

发明人： Omer Tripp ,  Marco Pistoia ,  Salvatore A. Guarnieri

IPC分类号： G06F11/36 ,  G06F21/57

CPC分类号： G06F11/3644 ,  G06F11/3624 ,  G06F11/3636 ,  G06F21/577 ,  G06F2221/033

摘要： An exemplary method includes performing a first static analysis to locate elements within a program and instrumenting the program to enable a subsequent dynamic analysis based on the located elements. The method includes executing the instrumented program and performing during execution analysis to determine individual sets of statements in the program affected by a corresponding element. The method includes partitioning the sets of statements into partitions based on one or more considerations, each partition including one or more of the elements. The method includes performing a second static analysis on the partitions of the program to produce results and outputting the results. The method may be performed for, e.g., security (e.g., taint) analysis, buffer overflow analysis, and typestate analysis. Apparatus and program products are also disclosed.

摘要翻译： 示例性方法包括执行第一静态分析以定位程序内的元素并且对该程序进行调整，以便能够基于所定位的元素进行后续的动态分析。 该方法包括执行检测程序并在执行分析期间执行以确定受相应元素影响的程序中的各组语句。 该方法包括基于一个或多个注意事项将语句集划分成分区，每个分区包括一个或多个元素。 该方法包括对程序的分区执行第二静态分析以产生结果并输出结果。 该方法可以用于例如安全性（例如，污点）分析，缓冲器溢出分析和类型化分析。 还公开了装置和程序产品。

公开(公告)号：US09171954B2

公开(公告)日：2015-10-27

申请号：US14537139

申请日：2014-11-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Eduard A. Cartier ,  Brian J. Greene ,  Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L21/02323 ,  H01L21/28017 ,  H01L27/1211 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

摘要翻译： 公开了FinFET结构和制造FinFET结构的方法。 该方法包括在FinFET结构的栅极堆叠上执行氧退火处理以引起Vt偏移。 氧退火工艺在侧壁下拉和硅化后进行。

公开(公告)号：US09171749B2

公开(公告)日：2015-10-27

申请号：US14078990

申请日：2013-11-13

申请人： International Business Machines Corporation

发明人： Bing Dang ,  Sarah H. Knickerbocker ,  Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Cornelia K. Tsang ,  Kevin R. Winstel

IPC分类号： H01L21/00 ,  H01L21/683 ,  H01L21/78

CPC分类号： H01L21/6836 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

摘要： A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.

摘要翻译： 一种去除处理器晶片的方法。 提供了具有多个半导体器件的处理器晶片和半导体器件晶片，半导体器件晶片具有有源表面侧和非活性表面侧。 将无定形碳层施加到处理器晶片的表面。 将粘合剂层施加到处理器晶片的无定形碳层和半导体器件晶片的有源表面侧中的至少一个。 处理器晶片通过粘合层或多层结合到半导体器件晶片。 将激光辐射施加到处理器晶片，以引起无定形碳层的加热，这又导致粘合剂层或层的加热。 然后，半导体器件晶片的多个半导体器件与处理器晶片分离。