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    Selective etching of silicon wafer
    5.
    发明授权
    Selective etching of silicon wafer 有权
    硅片的选择性蚀刻

    公开(公告)号：US09378966B2

    公开(公告)日：2016-06-28

    申请号：US14300679

    申请日：2014-06-10

    申请人： International Business Machines Corporation

    发明人： Brown C. Peethala ,  Spyridon Skordas ,  Da Song ,  Allan Upham ,  Kevin R. Winstel

    IPC分类号： H01L21/306 ,  H01L21/67 ,  C09K13/08 ,  H01L29/167

    CPC分类号： H01L21/30604 ,  C09K13/08 ,  H01L21/6708 ,  H01L29/167

    摘要： A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.

    摘要翻译： 提出了使用蚀刻溶液制备蚀刻溶液和减薄半导体晶片的方法。 该方法包括以约1:3:5的比例在溶液容器中产生氢氟酸，硝酸和乙酸的混合物的步骤; 使混合物与一个或多个硅晶片的部分反应，一个或多个硅晶片的部分以不小于1×1019原子/ cm3的量掺杂硼; 在与一个或多个硅晶片的硼掺杂部分反应之后收集混合物; 并将收集的混合物加入到溶液容器中以产生蚀刻溶液。

    WAFER TO WAFER ALIGNMENT
    6.
    发明申请
    WAFER TO WAFER ALIGNMENT 有权
    WAFER TO WAFER对准

    公开(公告)号：US20160178344A1

    公开(公告)日：2016-06-23

    申请号：US14576072

    申请日：2014-12-18

    申请人： International Business Machines Corporation

    发明人： Mukta G. Farooq ,  John A. Fitzsimmons ,  Spyridon Skordas

    IPC分类号： G01B7/30

    CPC分类号： G01B7/31 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

    摘要： Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.

    摘要翻译： 晶片对准包括第一半导体晶片和第二半导体晶片。 第一和第二半导体晶片具有用于使第一半导体晶片与第二半导体晶片对准的选择性激活对准阵列。 每个对准阵列包括对准结构，其包括连接到半导体器件的天线。 每个对准阵列中的天线被选择性地激活以用作电荷源或电荷感测接收器。 对准阵列位于半导体晶片的切口区域中。 当一个半导体晶片上的电荷源与另一个半导体晶片上的电荷感测接收体匹配时，半导体晶片对准。

    Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
    8.
    发明授权
    Reducing wafer bonding misalignment by varying thermal treatment prior to bonding 有权
    在接合之前通过改变热处理来减少晶片接合失准

    公开(公告)号：US09190303B2

    公开(公告)日：2015-11-17

    申请号：US14716236

    申请日：2015-05-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Douglas C. La Tulipe, Jr. ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

    IPC分类号： G01R31/26 ,  G06F19/00 ,  H01L21/67 ,  H01L23/00 ,  H01L21/324

    CPC分类号： H01L21/67259 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/324 ,  H01L22/12 ,  H01L22/20 ,  H01L24/83 ,  H01L24/94

    摘要： A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.

    摘要翻译： 对第一晶片制品的接合层进行热处理，并且在将第一晶片制品与第二晶片制品接合之前，分别根据第一和第二工艺参数对第二晶片制品的粘结层进行热处理。 测量第一和第二晶片制品中的第一和第二网格变形，并且在第一和第二格栅失真之间确定差异。 进行预测以将差异保持在规定的公差内。 第一处理参数和第二处理参数中的至少一个根据预测有条件地变化。 然后可以在通过其各自的结合层彼此粘合之前相对于另一对第一和第二晶片制品执行第一和第二晶片制品的热处理。

    DISTORTING DONOR WAFER TO CORRESPONDING DISTORTION OF HOST WAFER
    10.
    发明申请
    DISTORTING DONOR WAFER TO CORRESPONDING DISTORTION OF HOST WAFER 有权
    失真振荡器对主机波形的相应失真

    公开(公告)号：US20140356983A1

    公开(公告)日：2014-12-04

    申请号：US13908510

    申请日：2013-06-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Wei Lin ,  Spyridon Skordas ,  Tuan A. Vo

    IPC分类号： H01L21/02 ,  B32B38/18

    CPC分类号： H01L24/98 ,  B32B38/0012 ,  B32B38/1825 ,  B32B2457/14 ,  H01L21/02035 ,  H01L21/2007 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20 ,  H01L24/80 ,  Y10T156/1168 ,  Y10T156/17

    摘要： A method generally for improving wafer-to-wafer bonding alignment. Planar distortions of the bonding surface of a host wafer are determined. The bonding surface of a donor wafer is distorted such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface. Also, a method to separate bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair.

    摘要翻译： 通常用于改善晶片到晶片键合对准的方法。 确定主晶片的接合表面的平面变形。 施主晶片的接合表面变形，使得施主晶片接合表面的失真对应于所确定的主晶片接合表面的平面失真。 另外，分离粘合晶片的方法。 粘合晶片对安装在具有平坦卡盘面的第一和第二接合卡盘之间，第一接合卡盘面包括能够相对于彼此运动的可调节区域，至少相对运动的一部分沿着垂直于 平面第一粘接卡盘面。 第一面的可调节区域以协调的方式相对于彼此移动，使得在晶片对的接合面之间形成加宽的间隙。