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公开(公告)号：US20170345214A1
公开(公告)日：2017-11-30
申请号：US15168156
申请日：2016-05-30
申请人： Kwok Wai HUNG , Luhong LIANG , Xuejiao LIU
发明人： Kwok Wai HUNG , Luhong LIANG , Xuejiao LIU
CPC分类号： G06T3/4038 , H04N5/2258 , H04N5/23238
摘要： A hybrid-resolution panoramic VR generator places High-Resolution (HR) patches from a ring of HR cameras onto a 360-degree Low-Resolution (LR) image from a LR camera pointing upward from the ring into a panoramic mirror that captures the combined field of view of all the multiple HR cameras, but at a lower resolution. Ghosting artifacts caused by parallax errors between adjacent HR cameras are eliminated because object placement is determined by the 360-degree LR image. Each HR image is homographicly projected into 3 projections by grouping objects of different depths to obtain homographic matrixes. The 360-degree LR image is upscaled to HR and a query patch is searched in search windows in the three projections for up to two adjacent HR images. Best-matching patches are weighted by similarity with the query patch and blended to generate a reconstructed patch placed at the query patch location in a reconstructed HR panorama image.
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2.发明授权Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays 有权具有降低的AND和重构ADD逻辑阵列的直接数字合成器（DDS）的相位到幅度转换器公开(公告)号：US09021002B2
公开(公告)日：2015-04-28
申请号：US13760012
申请日：2013-02-05
发明人： Zhongzi Chen , Beiping Yan , Xiao Huo , Xiaowu Cai
CPC分类号： G06F1/0321 , G06F1/0328 , G06F1/0353 , G06F1/0356
摘要： A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.
摘要翻译： 直接数字合成器（DDS）的正弦波发生器将数字相位输入转换为数字正弦波输出。 正弦值和斜率存储在只读存储器（ROM）中用于第一象限中的粗略高位相位。 象限文件夹和分相器反映和反转第一象限的值，以产生所有四个象限的幅度。 每个正弦值和斜率都存储在较低相位位的范围内。 一个Delta位分离高位和低位相位。 Delta有条件地反转低位相位，正弦值和最终极性。 减少的AND逻辑阵列将斜率乘以有条件反相的下相位位。 然后，重建的ADD逻辑阵列会添加有条件反转的正弦值。 添加有条件反转的极性以产生最终正弦值。 基于Delta位的条件反演精简生成逻辑。
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3.发明授权Self-starting transistor-only full-wave rectifier for on-chip AC-DC conversion 有权用于片内AC-DC转换的自启动晶体管全波整流器公开(公告)号：US08964436B2
公开(公告)日：2015-02-24
申请号：US13653016
申请日：2012-10-16
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.
摘要翻译： 基于晶体管的全波桥式整流器适用于诸如由射频识别（RFID）设备接收的低交流输入电压。 避免了由桥二极管引起的电压降。 四个p沟道晶体管布置在跨过交流输入的桥中以产生内部电源电压。 比较器接收交流输入并控制升压驱动器的定时，该电压升压驱动器交替地驱动四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 在比较器和升压驱动器运行之前，四个二极管连接的晶体管与四个p沟道桥式晶体管并联连接，以在初始启动期间导通。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。 晶体管桥可以集成到系统芯片上。
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4.发明授权CMOS temperature sensor with sensitivity set by current-mirror and resistor ratios without limiting DC bias 有权CMOS温度传感器，灵敏度由电流镜和电阻比设置，不限制直流偏置公开(公告)号：US08864377B2
公开(公告)日：2014-10-21
申请号：US13416728
申请日：2012-03-09
IPC分类号： G01K7/01
摘要： An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.
摘要翻译： 片上温度传感器电路可以在使用PNP晶体管的标准互补金属氧化物半导体（CMOS）工艺中实现。 一对晶体管具有对电压敏感的集电极电流，直接和由于饱和电流。 缩放电阻连接到一个晶体管的发射极，其电压与另一个晶体管的发射极电压相比较，该误差放大器产生与绝对温度成比例的电流源的偏置电压，因为饱和电流灵敏度被减去。 电流被镜像以从输出端吸收电流通过乘法器电阻。 连接在乘法器电阻上的放大器将参考电压进行比较，以独立于温度敏感度设置直流偏置。 温度灵敏度与乘法器电阻和比例电阻的比例成正比，并乘以镜像因子。 还可以提供差分输出。
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5.发明申请CMOS Temperature Sensor with Sensitivity Set by Current-Mirror and Resistor Ratios without Limiting DC Bias 有权CMOS温度传感器，灵敏度由电流镜和电阻比设定，不限制直流偏置公开(公告)号：US20130235903A1
公开(公告)日：2013-09-12
申请号：US13416728
申请日：2012-03-09
IPC分类号： G01K7/01
摘要： An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.
摘要翻译： 片上温度传感器电路可以在使用PNP晶体管的标准互补金属氧化物半导体（CMOS）工艺中实现。 一对晶体管具有对电压敏感的集电极电流，直接和由于饱和电流。 缩放电阻连接到一个晶体管的发射极，其电压与另一个晶体管的发射极电压相比较，该误差放大器产生与绝对温度成比例的电流源的偏置电压，因为饱和电流灵敏度被减去。 电流被镜像以从输出端吸收电流通过乘法器电阻。 连接在乘法器电阻上的放大器将参考电压进行比较，以独立于温度敏感度设置直流偏置。 温度灵敏度与乘法器电阻和比例电阻的比例成正比，并乘以镜像因子。 还可以提供差分输出。
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6.发明申请REDUCED RESIDUAL OFFSET SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH CHOPPER TIMING AT END OF INTEGRATING PHASE BEFORE TRAILING EDGE 有权减少残留偏移SIGMA DELTA模拟数字转换器（ADC）在跟踪边缘之前的整合阶段结束时的切换时序公开(公告)号：US20130141264A1
公开(公告)日：2013-06-06
申请号：US13308737
申请日：2011-12-01
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译： 模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。 斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。 斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。 以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。 延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。 当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。 该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。
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7.发明申请公开(公告)号：US20120032718A1
公开(公告)日：2012-02-09
申请号：US12851209
申请日：2010-08-05
申请人： Chi Fat CHAN , Chien-Wei LIN , Gordon CHUNG
发明人： Chi Fat CHAN , Chien-Wei LIN , Gordon CHUNG
IPC分类号： H03L7/08
CPC分类号： H03L7/093 , H03L2207/06 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.
摘要翻译： 数字锁相环（DPLL）具有数字控制振荡器（DCO），用于产生由具有最高有效位（MSB）和最低有效位（LSB）的数字输入确定的输出时钟频率。 LSB由由控制时钟控制的脉冲宽度调制（PWM）控制器产生，控制时钟是输出时钟除以C。将参考时钟与输出时钟除以M的反馈时钟进行比较。PWM控制器 为每个参考时钟周期生成M / C LSB，并将它们并行并行串行传输LSB的并行到串行移位寄存器。 脉冲宽度由精细的数字环路滤波器确定，可以使用精细的时间分辨率对相位比较结果进行滤波。 粗略的数字环路滤波器使用粗略的时间分辨率从相位比较结果生成MSB。 通过随机选择高电平或低电平脉冲和随机调整脉冲宽度，对LSB波形进行抖动。
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8.发明申请MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译： 模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。
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9.发明授权Compact camera module with zoom and auto-focus actuators sharing the same rotating annular magnet with alternating thick and thin poles 有权具有变焦和自动对焦执行器的紧凑型相机模块共享相同的旋转环形磁体，交替厚薄极公开(公告)号：US09217841B2
公开(公告)日：2015-12-22
申请号：US13012928
申请日：2011-01-25
申请人： Kin Ming Fan , Kwok Sing Cheng
发明人： Kin Ming Fan , Kwok Sing Cheng
IPC分类号： H04N5/225 , G02B7/02 , G11B7/09 , G02B7/10 , G02B13/00 , H02K41/035 , G03B3/10 , G02B15/177
CPC分类号： G02B7/102 , G02B13/0045 , G02B13/009 , G02B15/177 , G03B3/10 , G03B2205/0046 , G03B2205/0069 , H02K41/0356
摘要： A compact camera modules has first, second, and third lens groups that move along an optical axis. A stepping motor is centered on the optical axis rather than offset from the optical axis. The motor has two coils that are fixed in place and a shared rotating magnet. The magnet is attached to a rotating guide that has slots to move the first and second lens groups as it rotates. The two coils are alternately energized to rotate the magnet, the rotating guide, and to move the first and second lens groups for zoom. The magnet has alternating thicker and thinner segments of opposite polarity. The thicker segments exert a greater force on an autofocus coil that is energized to move the third lens for the autofocus function. The same shared rotating magnet is used for both zoom and autofocus functions. A more compact design is possible using a shared magnet.
摘要翻译： 小型相机模块具有沿光轴移动的第一，第二和第三透镜组。 步进电机以光轴为中心，而不是偏离光轴。 电机有两个线圈固定在适当的位置和一个共享的旋转磁铁。 磁体附接到具有狭槽的旋转引导件，以在第一和第二透镜组旋转时移动第一和第二透镜组。 两个线圈交替地被激励以旋转磁体，旋转引导件，并且移动第一和第二透镜组以进行变焦。 磁体具有相反极性的交替较厚和较薄的段。 较厚的部分在自动聚焦线圈上施加更大的力，该自动聚焦线圈被激励以移动第三透镜进行自动对焦功能。 相同的共享旋转磁铁用于变焦和自动对焦功能。 使用共享磁铁可以实现更紧凑的设计。
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10.发明授权Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation 有权具有直接电荷传输和偏移消除的数字可编程增益放大器公开(公告)号：US09190961B1
公开(公告)日：2015-11-17
申请号：US14264252
申请日：2014-04-29
CPC分类号： H03F1/0233 , H03F1/0266 , H03F3/005 , H03F3/38 , H03F3/45071 , H03F3/45475 , H03F3/45605 , H03F2200/249 , H03F2200/405 , H03F2200/411 , H03F2200/471 , H03F2203/45116 , H03F2203/45512 , H03F2203/45536 , H03F2203/45544 , H03F2203/45616 , H03G1/0094 , H03G3/001 , H03G3/002
摘要： A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).
摘要翻译： 可编程增益放大器（PGA）具有可编程调节模拟放大器增益的数字值。 可变电容器具有通过数字值使能的几个开关子电容器。 启用子电容器在一个终端上的采样输入和虚拟地之间切换，并连接到另一个终端上的求和节点。 求和节点通过开关或通过存储偏移的双采样电容连接到运算放大器的反相输入。 当直接电荷转移发生时，反馈电容器在第二个时钟相位期间与采样电容并联，从而降低放大器的功耗。 反馈电容在第一个时钟阶段对采样输入进行采样。 PGA增益与使能子电容的电容之和成正比。 可以调整模拟前端（AFE）的传感器输入的增益，例如电心电图（ECG）。
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