公开(公告)号：US07674362B2

公开(公告)日：2010-03-09

申请号：US12061200

申请日：2008-04-02

申请人： Wen-Hung Hu

发明人： Wen-Hung Hu

IPC分类号： C25D17/00

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/0035 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/054 ,  H05K2203/0577 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for fabricating a conductive bump structure of a circuit board is disclosed. The circuit board with a plurality of electrical connection pads is provided. An insulating protective layer and a resist layer are successively applied on the circuit board, wherein openings are formed in the layers at positions corresponding to the pads to expose the pads. Then, a conductive layer is formed on surfaces of the resist layer and openings, and a metal layer is formed on the conductive layer via electroplating and filled in the openings. Subsequently, the metal layer and conductive layer formed on the resist layer are removed via thinning, so as to form metal bumps on the pads. After the resist layer is removed, the metal bumps are covered by an adhesive layer to form a conductive bump structure for electrically connecting the circuit board to the external electronic component.

摘要翻译： 公开了一种用于制造电路板的导电凸块结构的方法。 提供具有多个电连接垫的电路板。 绝缘保护层和抗蚀剂层依次施加在电路板上，其中在与焊盘相对应的位置的层中形成开口以露出焊盘。 然后，在抗蚀剂层和开口的表面上形成导电层，并且通过电镀在导电层上形成金属层并填充在开口中。 随后，通过减薄去除形成在抗蚀剂层上的金属层和导电层，以在焊盘上形成金属凸块。 在去除抗蚀剂层之后，金属凸块被粘合剂层覆盖，以形成用于将电路板电连接到外部电子部件的导电凸块结构。

公开(公告)号：US20100029047A1

公开(公告)日：2010-02-04

申请号：US12510379

申请日：2009-07-28

申请人： Shih-Ping Hsu ,  Wei Che Lin

发明人： Shih-Ping Hsu ,  Wei Che Lin

IPC分类号： H01L21/52

CPC分类号： H05K1/185 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/18162 ,  H05K3/4602 ,  H05K2201/10674

摘要： A method for fabricating a printed circuit board having semiconductor components embedded therein is provided. A carrier board having at least a predetermined hole area is provided. A plurality of through holes are formed in the surround of the predetermined hole area on the carrier board. A rectangular cavity is formed by punching to remove the predetermined hole area, and a plurality of through holes are formed around the rectangular cavity The through holes facilitate receipt of the semiconductor chip and filling of a fixing material in the rectangular cavity, to avoid displacement of the semiconductor chip in subsequent fabricating steps that would otherwise cause a drawback, that is, a wiring to be formed later is improperly electrically connected to the semiconductor chip.

摘要翻译： 提供了一种制造其中嵌有半导体元件的印刷电路板的方法。 提供具有至少预定孔面积的载板。 在承载板上的预定孔区域的周围形成有多个通孔。 通过冲压形成矩形空腔以去除预定的孔区域，并且在矩形空腔周围形成多个通孔。通孔便于半导体芯片的接收和矩形空腔中的固定材料的填充，以避免位移 否则将导致缺点的后续制造步骤中的半导体芯片，即稍后形成的布线不正确地电连接到半导体芯片。

公开(公告)号：US07629204B2

公开(公告)日：2009-12-08

申请号：US11432369

申请日：2006-05-12

申请人： Shih-Ping Hsu

发明人： Shih-Ping Hsu

IPC分类号： H01L21/00

CPC分类号： H01L24/19 ,  H01L23/3142 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/381 ,  Y10S438/964

摘要： A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on a surface of the electrode pads of the semiconductor chip, so as to form a rough structure on a surface of the semiconductor chip exposed by the opening of the carrier board. Thus, adhesion between the chip and a dielectric layer is improved during subsequently forming circuit build-up layers on the roughened surface of the semiconductor chip and on the surface of carrier board.

摘要翻译： 提出了一种嵌入式半导体芯片结构的表面粗糙化方法。 该方法包括：在载板的开口中提供具有开口并将半导体芯片安装的载体板，所述半导体芯片具有多个电极焊盘; 以及在半导体芯片的电极焊盘的表面上进行表面粗糙化处理，以便在由载体板的开口暴露的半导体芯片的表面上形成粗糙结构。 因此，随后在半导体芯片的粗糙化表面上和载体板的表面上形成电路堆积层期间，芯片和电介质层之间的粘合性得到改善。

公开(公告)号：US20090236750A1

公开(公告)日：2009-09-24

申请号：US12076470

申请日：2008-03-19

申请人： Kan-Jung Chia

发明人： Kan-Jung Chia

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107

摘要： A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.

摘要翻译： 公开了一种其中无芯基板具有与半导体芯片的直接电连接的封装结构及其制造方法。 该方法包括以下步骤：提供具有空腔的金属载板; 将具有多个电极焊盘的芯片放置在板的空腔中的有源表面上; 用用于固定芯片的粘合剂填充空腔; 在芯片的有效表面和同一侧的金属载体板的表面上形成焊料掩模，其中焊料掩模具有多个开口以暴露芯片的电极焊盘; 在焊料掩模上形成积层结构，并在开口中形成芯片的暴露的有源表面; 并移除金属载板。 在该方法中，金属载板可以支撑组合结构，从而避免翘曲。

公开(公告)号：US07582961B2

公开(公告)日：2009-09-01

申请号：US12020693

申请日：2008-01-28

申请人： Kan-Jung Chia ,  Shih-Ping Hsu

发明人： Kan-Jung Chia ,  Shih-Ping Hsu

IPC分类号： H01L23/12 ,  H01L23/053

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A package structure with circuit directly connected to semiconductor chip, which comprises: a carrier board, a semiconductor chip, and at least a built-up structure. The carrier board is formed with a through cavity therein. The semiconductor chip is mounted in the through cavity of the carrier board, and a lateral surface of the semiconductor chip is coated by an adhesive material which is not contacted by the carrier board. The built-up structure, which includes a dielectric layer, is disposed on the surface of the carrier board and an active surface of the semiconductor chip. Part surface of the dielectric layer is exposed by the through cavity. The present invention decreases warpage of the packaging structure resulting from asymmetrical built-up structures.

摘要翻译： 具有直接连接到半导体芯片的电路的封装结构，其包括：载板，半导体芯片和至少一个建立结构。 载板在其中形成有通孔。 半导体芯片安装在承载板的通孔中，并且半导体芯片的侧表面由不与载板接触的粘合材料涂覆。 包括电介质层的积层结构设置在载体板的表面和半导体芯片的有效表面上。 电介质层的部分表面被通孔暴露。 本发明减少了由不对称组合结构引起的包装结构翘曲。

公开(公告)号：US07553750B2

公开(公告)日：2009-06-30

申请号：US11559576

申请日：2006-11-14

申请人： Chao Wen Shih

发明人： Chao Wen Shih

IPC分类号： H01L21/44

CPC分类号： H05K3/243 ,  H01L21/4853 ,  H05K1/111 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2201/0989 ,  H05K2203/054

摘要： A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and second electrically conductive pads; forming a metal adhesive layer on the first and second electrically conductive pads; forming a conductive layer on the insulating protection layer and on the metal adhesive layer formed on the first and second electrically conductive pads, the conductive layer being electrical conductive to the first and second electrically conductive pads; forming on the conductive layer a resist layer having a plurality of openings for exposing the conductive layer on the second electrically conductive pads; and electroplating a conductive structure on the conductive layer on the second electrically conductive pads exposed from the openings.

摘要翻译： 公开了一种用于制造电路板的导电结构的方法。 该方法包括提供具有多个第一和第二导电焊盘的电路板; 在所述电路板上形成具有用于暴露所述第一和第二导电焊盘的多个开口的绝缘保护层; 在第一和第二导电焊盘上形成金属粘合剂层; 在绝缘保护层和形成在第一和第二导电焊盘上的金属粘合剂层上形成导电层，导电层与第一和第二导电焊盘导电; 在所述导电层上形成具有多个开口的抗蚀剂层，用于将所述导电层暴露在所述第二导电焊盘上; 以及在从所述开口暴露的所述第二导电焊盘上的所述导电层上电镀导电结构。

公开(公告)号：US20090102045A1

公开(公告)日：2009-04-23

申请号：US12285957

申请日：2008-10-17

申请人： Shih-Ping Hsu ,  Wen-Sung Chang ,  Chih-Kui Yang

发明人： Shih-Ping Hsu ,  Wen-Sung Chang ,  Chih-Kui Yang

IPC分类号： H01L23/12

CPC分类号： H01L23/50 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging substrate having capacitors embedded therein, comprising: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer, wherein each of the first circuit layers has a plurality of electrode plates and a plurality of circuits; an adhesive layer disposed between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein, pairs of the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form capacitors.

摘要翻译： 一种具有嵌入其中的电容器的封装衬底，包括：两个电容器配置层，每个电容器配置层分别由高电介质层和设置在高电介质层的两个相对表面上的两个第一电路层组成，其中每个第一电路层具有多个 电极板和多个电路; 设置在电容器配置层之间的粘合剂层，以粘附电容器配置层以形成芯板结构，其中每个第一电路层的电路之间的空间用粘合剂层填充; 以及穿过电容器配置层和粘合剂层的多个导电通孔，并分别电连接电容器配置层的电路; 其中，每个电容器配置层的相对表面上的电极板对成对平行并彼此对应以形成电容器。

公开(公告)号：US07514770B2

公开(公告)日：2009-04-07

申请号：US11467310

申请日：2006-08-25

申请人： Chia-Wei Chang ,  Chung-Cheng Lien

发明人： Chia-Wei Chang ,  Chung-Cheng Lien

IPC分类号： H01L23/02 ,  H05K3/30 ,  H05K1/16

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10515 ,  Y10T29/4913 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack structure of a carrier board embedded with semiconductor components and a method for fabricating the same are proposed. The stack structure includes first and second carrier boards having a through hole respectively, first and second semiconductors component disposed in through holes of the first and second semiconductor components respectively, and a dielectric layer structure clamped between the first carrier board and the second carrier board and having a first dielectric layer formed on the first carrier board and an inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and an inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer.

摘要翻译： 提出了嵌入半导体部件的载体板的堆叠结构及其制造方法。 叠层结构包括分别具有通孔的第一和第二载体板，分别设置在第一和第二半导体部件的通孔中的第一和第二半导体部件以及夹在第一载体板和第二载体板之间的电介质层结构， 具有形成在所述第一载体板上的第一电介质层和所述第一半导体部件的非活性表面并填充在所述第一载体板和所述第一半导体部件之间的间隙中，形成在所述第二载体板上的第二介电层， 第二半导体部件，并且填充在第二载体板和第二半导体部件之间的间隙中，以及夹在第一介电层和第二介电层之间的接合层。

公开(公告)号：US07507915B2

公开(公告)日：2009-03-24

申请号：US11462604

申请日：2006-08-04

申请人： Chia-Wei Chang ,  Lin-Yin Wong ,  Zao-Kuo Lai ,  Chung-Cheng Lien

发明人： Chia-Wei Chang ,  Lin-Yin Wong ,  Zao-Kuo Lai ,  Chung-Cheng Lien

IPC分类号： H05K1/16

CPC分类号： H05K1/185 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.

摘要翻译： 提出了嵌入半导体元件的载体板的堆叠结构及其制造方法。 提供了具有至少一个通孔的第一承载板和第二承载板。 第一保护层和第二保护层分别形成在第一和第二载体板的表面上。 至少一个第一半导体部件和至少一个第二半导体部件设置在第一和第二保护层上，分别容纳在第一和第二通孔中。 介电层层压在第一和第二载体板的表面之间，而不形成保护层。 因此，形成了具有减少的空间浪费的模块化封装结构。

公开(公告)号：US20090072384A1

公开(公告)日：2009-03-19

申请号：US12283538

申请日：2008-09-12

申请人： Lin-Yin Wong ,  Mao-Hua Yeh

发明人： Lin-Yin Wong ,  Mao-Hua Yeh

IPC分类号： H01L23/36

CPC分类号： H01L23/5389 ,  H01L23/3677 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.

摘要翻译： 本发明提供一种具有散热结构的封装基板，其包括具有第一表面的芯层和分别具有第一金属层和第二金属层的相对的第二表面。 第一金属层的一部分从穿透芯层和第二金属层的第二腔露出。 第二金属层的一部分从穿透芯层和第一金属层的第一腔露出。 各自具有其上具有电极焊盘的有源表面和相对的无效表面的半导体芯片被接收在第一和第二腔中，并分别附着到第二金属层和第一金属层。 设置在积聚电路结构中的导电通孔电连接到半导体芯片的电极焊盘。 穿透核心层和积聚电路结构的散热通孔连接金属层和接触垫。