公开(公告)号：US20060006422A1

公开(公告)日：2006-01-12

申请号：US11223740

申请日：2005-09-08

Applicant: Chih-Liang Chu ,  E-Tung Chou ,  Lin-Yin Wong

Inventor： Chih-Liang Chu ,  E-Tung Chou ,  Lin-Yin Wong

IPC: H01L27/148

CPC classification number: H01L24/16 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/243 ,  H05K2203/0361 ,  H05K2203/0542 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Abstract translation: 提供半导体封装基板，其在至少一个表面上具有多个接合焊盘并被导电膜覆盖。 形成在导电膜上的光致抗蚀剂层具有多个用于暴露与接合焊盘相对应的导电膜的部分的第一开口。 去除导电膜的暴露部分，以经由第一开口分别暴露接合焊盘。 暴露的焊盘分别镀有金属层。 然后，除去光致抗蚀剂层和被光致抗蚀剂层覆盖的导电膜的其余部分。 可以在基板的表面上形成具有多个第二开口的焊接掩模，并且允许分别在接合焊盘上的电镀金属层经由第二开口露出。

公开(公告)号：US07880296B2

公开(公告)日：2011-02-01

申请号：US12044271

申请日：2008-03-07

Applicant: Lin-Yin Wong ,  Zao-Kuo Lai

Inventor： Lin-Yin Wong ,  Zao-Kuo Lai

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H01L23/552 ,  H01L21/6835 ,  H01L23/3675 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2224/82

Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.

Abstract translation: 本发明提供一种具有嵌入其中的半导体芯片和形成在其上的保护金属层的芯片载体结构及其制造方法。 芯片载体结构包括嵌入芯片的载体结构和通过电镀在芯片嵌入载体结构的底表面和侧表面上形成的金属层。 金属层防止水分穿过芯片嵌入的载体结构的侧表面，以防止分层，提供屏蔽效果，并改善通过金属层的散热。

公开(公告)号：US20080246135A1

公开(公告)日：2008-10-09

申请号：US11976488

申请日：2007-10-25

Applicant: Lin-Yin Wong ,  Mao-Hua Yeh ,  Wang-Hsiang Tsai

Inventor： Lin-Yin Wong ,  Mao-Hua Yeh ,  Wang-Hsiang Tsai

IPC: H01L23/488

CPC classification number: H05K1/185 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18165 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/117 ,  H05K3/4602 ,  H05K3/4694 ,  H05K2201/09845 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.

Abstract translation: 公开了一种堆叠封装模块，其包括：第一封装结构，其包括嵌入其中的第一芯片的第一电路板，其中所述第一芯片具有多个电极焊盘; 第一电路板包括第一表面，相对的第二表面，多个暴露的电连接端，第一表面上的多个第一导电焊盘，多个导电通孔，以及至少一个电路层，其中电极 第一芯片的焊盘直接通过导电通孔和电路层电连接到电连接端和第一导电焊盘; 以及第二封装结构，其通过多个第一焊球电连接到所述第一封装结构，以使封装成封装。 本发明的堆叠式封装模块具有尺寸紧凑，性能高，灵活性高，可拆卸性好的特点。

公开(公告)号：US20080217762A1

公开(公告)日：2008-09-11

申请号：US12044271

申请日：2008-03-07

Applicant: Lin-Yin Wong ,  Zao-Kuo Lai

Inventor： Lin-Yin Wong ,  Zao-Kuo Lai

IPC: H01L23/48

CPC classification number: H01L23/552 ,  H01L21/6835 ,  H01L23/3675 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2224/82

Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.

Abstract translation: 本发明提供一种具有嵌入其中的半导体芯片和形成在其上的保护金属层的芯片载体结构及其制造方法。 芯片载体结构包括嵌入芯片的载体结构和通过电镀在芯片嵌入载体结构的底表面和侧表面上形成的金属层。 金属层防止水分穿过芯片嵌入的载体结构的侧表面，以防止分层，提供屏蔽效果，并改善通过金属层的散热。

公开(公告)号：US07050304B2

公开(公告)日：2006-05-23

申请号：US10772042

申请日：2004-02-03

Applicant: Shih-Ping Hsu ,  Lin-Yin Wong

Inventor： Shih-Ping Hsu ,  Lin-Yin Wong

IPC: H05K7/20

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/05599

Abstract: A heat sink structure with embedded electronic components is proposed, wherein a plurality of recessed cavities are formed on a heat sink for embedding the electronic components and receiving at least one semiconductor chip therein. This arrangement enhances electric performance of a semiconductor package with the above heat sink structure and improves heat dissipating efficiency of the semiconductor package.

Abstract translation: 提出了一种具有嵌入式电子部件的散热器结构，其中在散热器上形成多个凹腔，用于嵌入电子部件并在其中容纳至少一个半导体芯片。 这种布置提高了具有上述散热器结构的半导体封装的电性能，并提高了半导体封装的散热效率。

公开(公告)号：US07656015B2

公开(公告)日：2010-02-02

申请号：US12283538

申请日：2008-09-12

Applicant: Lin-Yin Wong ,  Mao-Hua Yeh

Inventor： Lin-Yin Wong ,  Mao-Hua Yeh

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L23/3677 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00

Abstract: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.

Abstract translation: 本发明提供一种具有散热结构的封装基板，其包括具有第一表面的芯层和分别具有第一金属层和第二金属层的相对的第二表面。 第一金属层的一部分从穿透芯层和第二金属层的第二腔露出。 第二金属层的一部分从穿透芯层和第一金属层的第一腔露出。 各自具有其上具有电极焊盘的有源表面和相对的无效表面的半导体芯片被接收在第一和第二腔中，并分别附着到第二金属层和第一金属层。 设置在积聚电路结构中的导电通孔电连接到半导体芯片的电极焊盘。 穿透核心层和积聚电路结构的散热通孔连接金属层和接触垫。

公开(公告)号：US20080230886A1

公开(公告)日：2008-09-25

申请号：US11976489

申请日：2007-10-25

Applicant: Lin-Yin Wong ,  Mao-Hua Yeh ,  Wang-Hsiang Tsai

Inventor： Lin-Yin Wong ,  Mao-Hua Yeh ,  Wang-Hsiang Tsai

IPC: H01L23/488

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18165 ,  H05K1/144 ,  H05K1/185 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/041 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads, the first circuit board comprises a first surface, an opposite second surface, a plurality of first conductive pads on the first surface, a plurality of second conductive pads on the second surface, a plurality of conductive vias, and at least one circuit layer, and the electrodes of the first chip directly electrically connect to the conductive pads on the surfaces of the circuit board through the conductive vias and the circuit layer within the circuit board; and a second package structure electrically connecting to the first package structure through a plurality of solder balls to make package on package. The stacked package module provided by this invention has characteristics of compact size, high performance, and high flexibility.

Abstract translation: 公开了一种堆叠封装模块，其包括：第一封装结构，其包括嵌入其中的第一芯片的第一电路板，其中所述第一芯片具有多个电极焊盘，所述第一电路板包括第一表面，相对的第二表面 ，第一表面上的多个第一导电焊盘，第二表面上的多个第二导电焊盘，多个导电通孔和至少一个电路层，并且第一芯片的电极直接电连接到导电焊盘 在电路板的表面上通过导电通孔和电路板内的电路层; 以及第二封装结构，其通过多个焊球电连接到所述第一封装结构，以使封装成封装。 本发明提供的堆叠封装模块具有尺寸紧凑，性能高，灵活性高的特点。

公开(公告)号：US20060261462A1

公开(公告)日：2006-11-23

申请号：US11133278

申请日：2005-05-20

Applicant: Zao-Kuo Lai ,  Lin-Yin Wong

Inventor： Zao-Kuo Lai ,  Lin-Yin Wong

IPC: H01L31/062 ,  H01L21/20

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/167 ,  H05K3/429 ,  H05K3/4644 ,  H05K2203/1453 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract translation: 提出了一种具有嵌入式电阻器的半导体封装基板及其制造方法。 首先，在其上设置有第一电路层的内部电路板，并且在第一电路层中形成多个电阻电极。 然后，在内部电路板上形成图形化的电阻材料，并电连接到电阻器电极，以精确地限定电阻器的电阻值。 随后，在具有图案化电阻材料的电路板的表面上涂覆至少一个绝缘层。 至少一个图案化的第二电路层形成在绝缘层上，并且通过形成在绝缘层中的多个导电通孔或通过电路板形成的电镀通孔形成在电阻器电极上。

公开(公告)号：US20060094156A1

公开(公告)日：2006-05-04

申请号：US10976878

申请日：2004-11-01

Applicant: Zao-Kuo Lai ,  Lin-Yin Wong

Inventor： Zao-Kuo Lai ,  Lin-Yin Wong

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/095 ,  H05K1/167 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2203/1453 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract translation: 提出了一种具有嵌入式电阻器的半导体封装基板及其制造方法。 首先，在其上设置有第一电路层的内部电路板，并且在第一电路层中形成多个电阻电极。 然后，在内部电路板上形成图形化的电阻材料，并电连接到电阻器电极，以精确地限定电阻器的电阻值。 随后，在具有图案化电阻材料的电路板的表面上涂覆至少一个绝缘层。 至少一个图案化的第二电路层形成在绝缘层上，并且通过形成在绝缘层中的多个导电通孔或通过电路板形成的电镀通孔形成在电阻器电极上。

公开(公告)号：US20050047094A1

公开(公告)日：2005-03-03

申请号：US10772042

申请日：2004-02-03

Applicant: Shih-Ping Hsu ,  Lin-Yin Wong

Inventor： Shih-Ping Hsu ,  Lin-Yin Wong

IPC: H01L23/367 ,  H01L25/065 ,  H05K7/20

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/05599

Abstract: A heat sink structure with embedded electronic components is proposed, wherein a plurality of recessed cavities are formed on a heat sink for embedding the electronic components and receiving at least one semiconductor chip therein. This arrangement enhances electric performance of a semiconductor package with the above heat sink structure and improves heat dissipating efficiency of the semiconductor package.

Abstract translation: 提出了一种具有嵌入式电子部件的散热器结构，其中在散热器上形成多个凹腔，用于嵌入电子部件并在其中容纳至少一个半导体芯片。 这种布置提高了具有上述散热器结构的半导体封装的电性能，并提高了半导体封装的散热效率。