公开(公告)号：US08883600B1

公开(公告)日：2014-11-11

申请号：US13725152

申请日：2012-12-21

申请人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US08748986B1

公开(公告)日：2014-06-10

申请号：US13559554

申请日：2012-07-26

申请人： Lucian Shifren ,  Pushkar Ranade

发明人： Lucian Shifren ,  Pushkar Ranade

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/786 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78696

摘要： Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.

摘要翻译： 其结构及其制造方法涉及形成在SOI衬底上的改进的绝缘体上半导体（SOI）晶体管。 改进的SOI晶体管包括在源极和漏极之间延伸的基本上未掺杂的沟道，位于基本上未掺杂沟道下方的可选阈值电压设置区域和位于阈值电压设置区域下方的屏蔽区域。 可以使用屏蔽区域和/或阈值电压设置区域的位置和/或掺杂剂浓度来调整改进的SOI晶体管的阈值电压而无需光晕注入或阈值电压注入到沟道中。

公开(公告)号：US20140119099A1

公开(公告)日：2014-05-01

申请号：US14068756

申请日：2013-10-31

申请人： Suvolta, Inc.

发明人： Lawrence T. Clark ,  Lucian Shifren ,  Richard S. Roy

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C5/146 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4091 ,  H01L27/10897

摘要： A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.

摘要翻译： 动态随机存取存储器（DRAM）可以包括至少一个DRAM单元阵列，其包括多个DRAM单元，每个DRAM单元包括存储电容器和存取晶体管; 身体偏置控制电路，被配置为从偏置电源电压产生体偏置电压，所述体偏置电压不同于所述DRAM的电源电压; 以及形成在与至少一个DRAM阵列相同的衬底中的外围电路，所述外围电路包括具有耦合以接收体偏置电压的体的深度耗尽的通道（DDC）晶体管，每个DDC晶体管具有形成的第一导电类型的屏蔽区域 在基本上未掺杂的通道区域之下。

公开(公告)号：US20140038386A1

公开(公告)日：2014-02-06

申请号：US14046147

申请日：2013-10-04

申请人： SuVolta, Inc.

发明人： Lance S. Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/04 ,  H01L21/82 ,  H01L29/66

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

摘要翻译： 制造使用碳掺杂硅层的场效应晶体管的方法，用于基本上减少形成在基本上未掺杂的沟道层下面的掺杂屏蔽层的扩散，包括形成原位外延碳掺杂的硅衬底，其被掺杂以形成屏蔽层 碳掺杂硅衬底并且在碳掺杂硅衬底上形成基本上未掺杂的硅层。 该方法可以包括在筛网层下方注入碳并在筛网层上方形成薄层原位外延碳掺杂硅。 屏幕层可以形成在硅衬底层或碳掺杂硅衬底中。

公开(公告)号：US08599623B1

公开(公告)日：2013-12-03

申请号：US13336434

申请日：2011-12-23

申请人： Lawrence T Clark ,  Richard S Roy

发明人： Lawrence T Clark ,  Richard S Roy

IPC分类号： G11C7/00

CPC分类号： G01R31/2607 ,  G01R31/275 ,  G01R35/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/41 ,  G11C29/026 ,  G11C29/1201 ,  G11C29/48

摘要： An integrated circuit device can include a plurality of test elements, each comprising at least one first switch coupled between a node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and an output node; wherein the forced voltage node is coupled to receive a forced voltage substantially the same as a test voltage applied to the output node in a test mode.

摘要翻译： 集成电路设备可以包括多个测试元件，每个测试元件包括耦合在测试部分内的节点和中间节点之间的至少一个第一开关，耦合在中间节点和强制电压节点之间的测试开关，以及第二开关 耦合在中间节点和输出节点之间; 其中所述强制电压节点被耦合以接收与在测试模式中施加到所述输出节点的测试电压基本相同的强制电压。

公开(公告)号：US08461875B1

公开(公告)日：2013-06-11

申请号：US13030939

申请日：2011-02-18

申请人： Scott E. Thompson ,  Lawrence T. Clark

发明人： Scott E. Thompson ,  Lawrence T. Clark

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H03K19/0013 ,  G11C11/412 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/11807 ,  H01L29/1095 ,  H03K19/0948

摘要： Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

公开(公告)号：US08264017B2

公开(公告)日：2012-09-11

申请号：US13218600

申请日：2011-08-26

申请人： Srinivasa R. Banna

发明人： Srinivasa R. Banna

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/808 ,  H01L29/0692 ,  H01L29/66901

摘要： A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.

摘要翻译： 结场效应晶体管包括沟道区，耦合到沟道区的栅极区，耦合到栅极区和沟道区的阱抽头区，以及耦合到阱抽头区和沟道区的阱区。 通过这种结构实现双栅极操作，因为施加到栅极区域的电压也通过阱抽头区域施加到阱区域，以便从栅极区域和阱区域两者打开沟道。

公开(公告)号：US20110074498A1

公开(公告)日：2011-03-31

申请号：US12708497

申请日：2010-02-18

申请人： Scott E. Thompson ,  Damodar R. Thummalapally

发明人： Scott E. Thompson ,  Damodar R. Thummalapally

IPC分类号： G05F1/10 ,  H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8236

CPC分类号： H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

摘要： A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.

摘要翻译： 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。

公开(公告)号：US07847354B1

公开(公告)日：2010-12-07

申请号：US12366791

申请日：2009-02-06

申请人： Damodar R. Thummalapally

发明人： Damodar R. Thummalapally

IPC分类号： H01L27/01 ,  H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/808

摘要： A semiconductor device comprises a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon. The four terminal JFET comprises a source region, a drain region, a channel region, a front gate region, and a back gate region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET comprises a source region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure, and a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET further comprises a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET also comprises a gate region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. A gate-to-channel junction of the three terminal JFET is formed deep enough in the semiconductor layer such that the channel region of the three terminal JFET abuts an insulating layer of the semiconductor-on-insulator structure.

摘要翻译： 半导体器件包括部分耗尽的绝缘体上半导体结构，其上结构有三端JFET和四端JFET。 四端JFET包括形成在部分耗尽的绝缘体上半导体结构的半导体层中的源极区，漏极区，沟道区，前栅区和背栅区。 三端JFET包括形成在部分耗尽的绝缘体上半导体结构的半导体层中的源极区和与源区间隔开并形成在部分耗尽的绝缘体上半导体结构的半导体层中的漏极区 。 三端JFET还包括在源区和漏区之间的沟道区，并形成在部分耗尽的绝缘体上半导体结构的半导体层中。 三端JFET还包括在部分耗尽的绝缘体上半导体结构的半导体层中形成的栅极区。 三端JFET的栅极至沟道结形成在半导体层中足够深，使得三端JFET的沟道区域与绝缘体上半导体结构的绝缘层相邻。

公开(公告)号：US07843721B1

公开(公告)日：2010-11-30

申请号：US12284037

申请日：2008-09-18

申请人： Richard K. Chou ,  Damodar R. Thummalapally

发明人： Richard K. Chou ,  Damodar R. Thummalapally

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.

摘要翻译： 已经公开了包括具有结型场效应晶体管（JFET）的静态随机存取存储器（SRAM）单元的存储器件。 存储单元包括用于以逻辑电平驱动位线的第一双极结型晶体管（BJT），该逻辑电平具有在SRAM单元操作的电位范围之外的电位。 包括电平转换器电路的放大器对由位线提供的数据提供电平移位操作，以提供在SRAM单元操作的电位范围内具有电压摆幅的电平移位数据。 电平转换器电路包括第二BJT。 以这种方式，可以提供包括JFET的SRAM单元的快速读取操作。