公开(公告)号：US20120088318A1

公开(公告)日：2012-04-12

申请号：US13269658

申请日：2011-10-10

申请人： Hsiang-Szu CHANG ,  Nien-Tze YEH ,  Kuen-Pu LU ,  Chao-Cheng WANG

发明人： Hsiang-Szu CHANG ,  Nien-Tze YEH ,  Kuen-Pu LU ,  Chao-Cheng WANG

IPC分类号： H01L33/48

CPC分类号： H01L33/0079 ,  H01L33/007 ,  H01L33/20 ,  H01L33/22

摘要： A method for fabricating a vertical light-emitting diode comprises forming a stack including a plurality of epitaxial layers on a patterned first substrate, placing a second substrate on the stack, removing the first substrate to expose the first surface, planarizing a first surface of the stack that was in contact with the patterned first substrate and has a pattern corresponding to a pattern provided on the first substrate to form a planarized second surface, and forming a first electrode in contact with a side of the second substrate that is opposite to the stack, and a second electrode in contact with the second surface of the stack. A roughening step can be performed to form uneven surface portions on a region of the second surface for improving light emission through the second surface of the stack.

摘要翻译： 一种用于制造垂直发光二极管的方法包括在图案化的第一衬底上形成包括多个外延层的堆叠，将第二衬底放置在堆叠上，去除第一衬底以暴露第一表面，平坦化第一衬底的第一表面 堆叠，其与图案化的第一基板接触并且具有对应于设置在第一基板上的图案的图案以形成平坦化的第二表面，并且形成与第二基板的与堆叠相反的一侧接触的第一电极 以及与所述堆叠的第二表面接触的第二电极。 可以进行粗糙化步骤以在第二表面的区域上形成不均匀的表面部分，以改善通过叠层的第二表面的发光。

公开(公告)号：US07462505B2

公开(公告)日：2008-12-09

申请号：US11063479

申请日：2005-02-23

申请人： Chia Ming Lee ,  Tsung Liang Cheng ,  I Ling Chen ,  Yu Chuan Liu ,  Jen Inn Chyi

发明人： Chia Ming Lee ,  Tsung Liang Cheng ,  I Ling Chen ,  Yu Chuan Liu ,  Jen Inn Chyi

IPC分类号： H01L21/00

CPC分类号： C30B29/406 ,  C30B25/02 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02661

摘要： In a method of forming a crystalline GaN-based material, a first nucleation layer is formed on a substrate at a first temperature, followed with forming a second nucleation layer at a second temperature different from the first temperature. The first and second nucleation layers are composed of AlxInyGa(1-x-y)N. Subsequently, a layer of a crystalline GaN-based compound is epitaxy grown on the second nucleation layer.

摘要翻译： 在形成结晶GaN基材料的方法中，在第一温度下在基板上形成第一成核层，随后在与第一温度不同的第二温度下形成第二成核层。 第一和第二成核层由Al x In y Ga（1-x-y）N组成。 随后，在第二成核层上生长一层结晶的GaN基化合物外延生长。

公开(公告)号：USD559802S1

公开(公告)日：2008-01-15

申请号：US29257816

申请日：2006-04-11

申请人： Wen-Chieh Hsu ,  Liang-Jyi Yan ,  Jenn-Hwa Fu

设计人： Wen-Chieh Hsu ,  Liang-Jyi Yan ,  Jenn-Hwa Fu

公开(公告)号：US07166483B2

公开(公告)日：2007-01-23

申请号：US10870347

申请日：2004-06-17

申请人： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

发明人： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

IPC分类号： H01L21/00

CPC分类号： H01L33/38 ,  H01L33/46 ,  H01L33/62 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A light-emitting device comprises a multi-layer structure including one or more active layer configured to irradiate light in response to the application of an electric signal, a transparent passivation layer laid over an outmost surface of the multi-layer stack, a reflector layer laid over the passivation layer, and a plurality of electrode pads coupled with the multi-layer structure. In a manufacture process of the light-emitting device, the reflector layer and the passivation layer are patterned to form at least one opening exposing an area of the multi-layer structure. One electrode pad is formed through the opening of the reflector layer and the passivation layer to connect with the multi-layer structure.

摘要翻译： 发光装置包括多层结构，其包括响应于电信号的施加而被配置为照射光的一个或多个有源层，布置在多层堆叠的最外表面上的透明钝化层，反射层 铺设在钝化层上，以及与多层结构耦合的多个电极焊盘。 在发光器件的制造工艺中，对反射层和钝化层进行构图以形成暴露多层结构区域的至少一个开口。 一个电极焊盘通过反射层的开口和钝化层形成，以与多层结构连接。

公开(公告)号：US20060121700A1

公开(公告)日：2006-06-08

申请号：US11005193

申请日：2004-12-06

申请人： Lung-Han Peng ,  Han-Ming Wu ,  Jing-Yi Lin

发明人： Lung-Han Peng ,  Han-Ming Wu ,  Jing-Yi Lin

IPC分类号： H01L21/84 ,  H01L21/20

CPC分类号： H01L21/02241 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3143 ,  H01L21/31679 ,  H01L29/78681

摘要： A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

摘要翻译： 在制造半导体器件中形成栅极绝缘体的方法包括进行光辅助电化学处理以在半导体器件的氮化镓层上形成栅极绝缘层，其中栅极绝缘层包括氮氧化镓和镓 并进行快速热退火处理。 光辅助电化学方法在约5.5和7.5之间的pH下使用包括缓冲CH 3 COOH的电解质浴。 快速热退火工艺在O 2 O 2环境中在约500℃至800℃的温度下进行。

公开(公告)号：US20150123160A1

公开(公告)日：2015-05-07

申请号：US14072915

申请日：2013-11-06

申请人： TEKCORE CO., LTD.

发明人： Hai-Wen Hsu ,  Hsin-Hsiang Tseng ,  Ruei-Ming Yang

IPC分类号： H01L33/38 ,  H01L33/48

CPC分类号： H01L25/0753 ,  H01L33/62 ,  H01L2224/14 ,  H01L2924/19107

摘要： A flip chip light-emitting diode (LED) package structure includes a circuit board, an electrical conducting layer and a plurality of flip chip light-emitting elements. The circuit board includes a bearing surface. The electrical conducting layer is formed on the bearing surface, and includes a plurality of electrical connection regions independent of each other. Each flip chip light-emitting element includes a p-type electrode and an n-type electrode. The p-type electrodes and the n-type electrodes of the flip chip light-emitting elements are electrically connected to the electrical connection regions, so that the flip chip light-emitting elements are electrically connected in series to form a package structure. During packaging of the flip chip light-emitting elements, the structure formed by the serial connection forms a circuit that can withstand a high voltage, and further reduce the current.

摘要翻译： 倒装芯片发光二极管（LED）封装结构包括电路板，导电层和多个倒装芯片发光元件。 电路板包括一个支承面。 导电层形成在轴承表面上，并且包括彼此独立的多个电连接区域。 每个倒装芯片发光元件包括p型电极和n型电极。 倒装芯片发光元件的p型电极和n型电极电连接到电连接区域，使得倒装芯片发光元件串联电连接以形成封装结构。 在封装倒装芯片发光元件的过程中，通过串联形成的结构形成可承受高电压的电路，并进一步降低电流。

公开(公告)号：US07977254B2

公开(公告)日：2011-07-12

申请号：US12931361

申请日：2007-06-27

申请人： Lung-Han Peng ,  Han-Ming Wu ,  Jing-Yi Lin

发明人： Lung-Han Peng ,  Han-Ming Wu ,  Jing-Yi Lin

IPC分类号： H01L21/31

CPC分类号： H01L21/02241 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3143 ,  H01L21/31679 ,  H01L29/78681

摘要： A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

摘要翻译： 在制造半导体器件中形成栅极绝缘体的方法包括进行光辅助电化学处理以在半导体器件的氮化镓层上形成栅极绝缘层，其中栅极绝缘层包括氮氧化镓和镓 并进行快速热退火处理。 光辅助电化学方法使用包含缓冲CH 3 COOH的电解质浴，pH在约5.5和7.5之间。 快速热退火过程在氧气环境中在约500℃至800℃之间的温度下进行。

公开(公告)号：US20110006307A1

公开(公告)日：2011-01-13

申请号：US12828447

申请日：2010-07-01

申请人： Guan-Ting CHEN ,  Chia-Ming LEE

发明人： Guan-Ting CHEN ,  Chia-Ming LEE

IPC分类号： H01L29/872 ,  H01L29/205 ,  H01L21/329 ,  H01L29/20

CPC分类号： H01L29/872 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/66212

摘要： A group III-nitride semiconductor Schottky diode comprises a conducting substrate having a first surface, a stack of multiple layers including a buffer layer and a semiconductor layer sequentially formed on the first surface, wherein the semiconductor layer comprises a group III nitride compound, a first electrode on the semiconductor layer, and a second electrode formed in contact with the first surface at a position adjacent to the stack of multiple layers. In other embodiments, the application also describes a method of fabricating the group III-nitride semiconductor Schottky diode.

摘要翻译： III族氮化物半导体肖特基二极管包括具有第一表面的导电衬底，包括缓冲层的多层叠层和顺序地形成在第一表面上的半导体层，其中半导体层包括III族氮化物化合物，第一 电极，以及在与多层叠层相邻的位置形成为与第一表面接触的第二电极。 在其它实施例中，本申请还描述了制造III族氮化物半导体肖特基二极管的方法。

公开(公告)号：US07645624B2

公开(公告)日：2010-01-12

申请号：US11980472

申请日：2007-10-31

申请人： Yu-Chuan Liu ,  Hung-Cheng Lin ,  Wen-Chieh Hsu ,  Chia-Ming Lee ,  Jenn-Hwa Fu

发明人： Yu-Chuan Liu ,  Hung-Cheng Lin ,  Wen-Chieh Hsu ,  Chia-Ming Lee ,  Jenn-Hwa Fu

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L33/22 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02395 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007

摘要： A method for self bonding epitaxy includes forming a passivation layer on a substrate surface of a semiconductor lighting element; etching to form recesses and protrusive portions with the passivation layer located thereon; starting forming epitaxy on the bottom surface of the recesses; filling the recesses with an Epi layer; then covering the protrusive portions and starting self bonding upwards the epitaxy to finish the Epi layer structure. Such a self bonding epitaxy growing technique can prevent cavity generation caused by parameter errors of the epitaxy and reduce defect density, and improve the quality of the Epi layer and increase internal quantum efficiency.

摘要翻译： 一种用于自粘合外延的方法包括在半导体照明元件的衬底表面上形成钝化层; 蚀刻以形成具有位于其上的钝化层的凹部和突出部分; 开始在凹槽的底表面上形成外延; 用Epi层填充凹槽; 然后覆盖突起部分并开始自身向上附着外延以完成Epi层结构。 这种自粘合外延生长技术可以防止由外延参数误差引起的空腔产生并降低缺陷密度，提高Epi层的质量并提高内部量子效率。

公开(公告)号：US20090111202A1

公开(公告)日：2009-04-30

申请号：US11980472

申请日：2007-10-31

申请人： Yu-Chuan Liu ,  Hung-Cheng Lin ,  Wen-Chieh Hsu ,  Chia-Ming Lee ,  Jenn-Hwa Fu

发明人： Yu-Chuan Liu ,  Hung-Cheng Lin ,  Wen-Chieh Hsu ,  Chia-Ming Lee ,  Jenn-Hwa Fu

IPC分类号： H01L33/00

CPC分类号： H01L33/22 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02395 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007

摘要： A method for self bonding epitaxy includes forming a passivation layer on a substrate surface of a semiconductor lighting element; etching to form recesses and protrusive portions with the passivation layer located thereon; starting forming epitaxy on the bottom surface of the recesses; filling the recesses with an Epi layer; then covering the protrusive portions and starting self bonding upwards the epitaxy to finish the Epi layer structure. Such a self bonding epitaxy growing technique can prevent cavity generation caused by parameter errors of the epitaxy and reduce defect density, and improve the quality of the Epi layer and increase internal quantum efficiency.

摘要翻译： 一种用于自粘合外延的方法包括在半导体照明元件的衬底表面上形成钝化层; 蚀刻以形成具有位于其上的钝化层的凹部和突出部分; 开始在凹槽的底表面上形成外延; 用Epi层填充凹槽; 然后覆盖突起部分并开始自身向上附着外延以完成Epi层结构。 这种自粘合外延生长技术可以防止由外延参数误差引起的空腔产生并降低缺陷密度，提高Epi层的质量并提高内部量子效率。