利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.012 秒)

    Method for color signal gamut mapping and saturation boosting
    2.
    发明授权
    Method for color signal gamut mapping and saturation boosting 有权
    彩色信号色域映射和饱和提升方法

    公开(公告)号：US08259125B2

    公开(公告)日：2012-09-04

    申请号：US13302317

    申请日：2011-11-22

    申请人： Rajeev Ramanath ,  Larry L. Jenkins

    发明人： Rajeev Ramanath ,  Larry L. Jenkins

    IPC分类号： G09G5/00 ,  G09G5/02 ,  G06K9/00 ,  H04N5/46 ,  H04N5/74 ,  H04N1/46 ,  G02F1/07 ,  G03F3/38 ,  G03F3/08 ,  G09G3/16 ,  G06K9/36 ,  G06K9/40 ,  H04N5/00 ,  H04N9/28

    CPC分类号： G09G5/02 ,  G09G3/001 ,  G09G3/346 ,  G09G2340/06

    摘要： Methods for gamut mapping and boosting a color saturation of a color signal having multiple colors and a color value for each color. An example method includes mapping each color from a first to a second color space, adjusting each color in the mapped color signal including boosting a color saturation; determining a maximum color value of the color signal; and, in response to a determining that the maximum color value exceeds a maximum displayable color value, setting the color value of the color having the maximum color value to be equal to the maximum displayable color value and scaling color values of colors not having the maximum color value.

    摘要翻译： 用于色域映射和提升具有多种颜色的彩色信号的颜色饱和度和每种颜色的颜色值的方法。 一种示例性方法包括将每种颜色从第一颜色空间映射到第二颜色空间，调整所映射的颜色信号中的每种颜色，包括增加色彩饱和度; 确定所述颜色信号的最大颜色值; 并且响应于确定最大颜色值超过最大可显示颜色值，将具有最大颜色值的颜色的颜色值设置为等于最大可显示颜色值和不具有最大颜色的颜色的缩放颜色值 颜色值。

    Switching System with Reduced EMI
    4.
    发明申请
    Switching System with Reduced EMI 有权
    具有降低EMI功能的开关系统

    公开(公告)号：US20100060340A1

    公开(公告)日：2010-03-11

    申请号：US12206905

    申请日：2008-09-09

    申请人： Richard Knight Hester ,  Patrick Peter Siniscalchi

    发明人： Richard Knight Hester ,  Patrick Peter Siniscalchi

    IPC分类号： H03K17/28

    CPC分类号： H03K17/164 ,  H03K17/163 ,  H03K17/6871 ,  H03K2217/0045

    摘要： Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

    摘要翻译： 本文公开了用于具有降低的EMI的开关模式电子电路的各种装置，方法和系统。 例如，本发明的一些实施例提供了包括连接在电源和输出之间的电源，输出和复合开关的装置。 复合开关包括并联连接的多个晶体管，具有多个开关闭合输出的开关闭合延迟线，每个开关闭合输出分别连接到多个晶体管之一的控制输入端，开关延迟线具有多个开关开路 每个连接到多个开关闭合输出中的一个的输出。 开关闭合延迟线和开关断开延迟线以按顺序以交错顺序打开多个晶体管的顺序连接，并且以反向交错的顺序关闭多个晶体管。

    Semiconductor storage device
    5.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US5862086A

    公开(公告)日：1999-01-19

    申请号：US701348

    申请日：1996-08-22

    申请人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

    发明人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/785 ,  G11C29/804 ,  G11C29/808

    摘要： A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

    摘要翻译： 半导体存储装置具有用于故障地址的存储电路和对应于存储电路的多个冗余字线。 存储电路适于存储选择冗余字线所需的故障地址。 故障地址与比较器存储器访问时的地址输入进行比较。 使用从比较器产生的符合信号和包含在输入地址中的预定地址信号，缺陷消除电路选择一个冗余字线来代替有缺陷的字线。

    Link width scaling across multiple retimer devices
    6.
    发明授权
    Link width scaling across multiple retimer devices 审中-公开

    公开(公告)号：US10671553B2

    公开(公告)日：2020-06-02

    申请号：US15858366

    申请日：2017-12-29

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Pakyiu Leung ,  Casey Thomas Morrison

    IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/12 ,  G06F13/42 ,  G06F13/364 ,  G06F1/10

    摘要： Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.

    Bandwidth mismatch estimation for time interleaved ADCs
    7.
    发明授权
    Bandwidth mismatch estimation for time interleaved ADCs 有权
    时间交错ADC的带宽失配估计

    公开(公告)号：US07916051B1

    公开(公告)日：2011-03-29

    申请号：US12572831

    申请日：2009-10-02

    申请人： Charles K. Sestok ,  Fernando A. Mujica

    发明人： Charles K. Sestok ,  Fernando A. Mujica

    IPC分类号： H03M1/10

    CPC分类号： H03M1/1061 ,  H03M1/1215

    摘要： With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced.

    摘要翻译： 采用高速，高分辨率时间交错（TI）模数转换器（ADC），各种ADC分支之间的带宽不匹配可能会造成重大问题。 以前，虽然没有找到足够的解决方案。 这里提供了一种方法和装置，可以计算和补偿TI ADC中的带宽不匹配，从而实现高速，高分辨率TI ADC的生产。

    Biasing scheme for low-voltage MOS cascode current mirrors
    8.
    发明授权
    Biasing scheme for low-voltage MOS cascode current mirrors 有权
    低压MOS共源共栅电流镜的偏置方案

    公开(公告)号：US07639081B2

    公开(公告)日：2009-12-29

    申请号：US11742117

    申请日：2007-04-30

    申请人： Abhijith Arakali ,  Sunil Rafeeque

    发明人： Abhijith Arakali ,  Sunil Rafeeque

    IPC分类号： H03F3/04

    CPC分类号： H03F1/301 ,  G05F3/262 ,  H03F3/345 ,  H03F2200/447 ,  H03F2200/456 ,  H03F2200/513 ,  H03F2200/91

    摘要： A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.

    摘要翻译： 提出了一种用于偏置复合共源共栅电流镜（CCCM）的电路和方法，其使得能够在输出端实现高电压摆幅和精确的电流镜像。 CCCM具有可能是不同技术类型的镜像晶体管和共源共栅晶体管。 CCCM的输入支路上的反射镜晶体管的漏极 - 源极电压Vds保持在由偏置电路产生的电压Vov; Vov是CCCM的输入镜像晶体管的过驱动电压，Vov的值由偏置电路和反馈放大器维持，使得反射镜晶体管保持在其有源区的边缘，超过制造偏差和轨迹甚至 超出操作条件，如温度和供应变化。 反馈放大器驱动共源共栅晶体管的栅极，并使用其反馈节点将Vds保持在Vov。