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1.发明授权Shift register that suppresses operation failure due to transistor threshold variations, and liquid crystal driving circuit including the shift register 失效移位寄存器，用于抑制晶体管阈值变化引起的操作故障，液晶驱动电路包括移位寄存器公开(公告)号：US07336254B2
公开(公告)日：2008-02-26
申请号：US11076823
申请日：2005-03-09
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G11C19/184
摘要： A shift register having a plurality of stages connected in cascade shifts an output signal by a plurality of clocks having different phases. Each of the stage includes an input diode to which a signal is input from a preceding stage, a capacitor for holding charge having a voltage level of the input signal, a first transistor that is turned on or off by the held voltage level to output an output signal to a following stage in synchronization with a clock signal, and a second transistor connected between the input diode and an output terminal. A control electrode of the second transistor is connected to the input diode in the following stage. The second transistor has a clamping function for discharging the accumulated charge and turning off the first transistor when the clock signal is phase-shifted.
摘要翻译： 具有串联连接的多个级的移位寄存器通过具有不同相位的多个时钟偏移输出信号。 每个级包括从前级输入信号的输入二极管，用于保持具有输入信号的电压电平的电荷的电容器，通过保持的电压电平导通或截止的第一晶体管，以输出 输出信号与时钟信号同步的后级，以及连接在输入二极管和输出端之间的第二晶体管。 第二晶体管的控制电极在下一级连接到输入二极管。 当时钟信号相移时，第二晶体管具有用于放电累积电荷并关断第一晶体管的钳位功能。
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2.发明申请Shift register that suppresses operation failure due to transistor threshold variations, and liquid crystal driving circuit including the shift register 失效移位寄存器，用于抑制晶体管阈值变化引起的操作故障，液晶驱动电路包括移位寄存器公开(公告)号：US20050212746A1
公开(公告)日：2005-09-29
申请号：US11076823
申请日：2005-03-09
CPC分类号： G09G3/3677 , G11C19/184
摘要： A shift register having a plurality of stages connected in cascade shifts an output signal by a plurality of clocks having different phases. Each of the stage includes an input diode to which a signal is input from a preceding stage, a capacitor for holding charge having a voltage level of the input signal, a first transistor that is turned on or off by the held voltage level to output an output signal to a following stage in synchronization with a clock signal, and a second transistor connected between the input diode and an output terminal. A control electrode of the second transistor is connected to the input diode in the following stage. The second transistor has a clamping function for discharging the accumulated charge and turning off the first transistor when the clock signal is phase-shifted.
摘要翻译： 具有串联连接的多个级的移位寄存器通过具有不同相位的多个时钟偏移输出信号。 每个级包括从前级输入信号的输入二极管，用于保持具有输入信号的电压电平的电荷的电容器，通过保持的电压电平导通或截止的第一晶体管，以输出 输出信号与时钟信号同步的后级，以及连接在输入二极管和输出端之间的第二晶体管。 第二晶体管的控制电极在下一级连接到输入二极管。 当时钟信号相移时，第二晶体管具有用于放电累积电荷并关断第一晶体管的钳位功能。
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公开(公告)号：US5869351A
公开(公告)日：1999-02-09
申请号：US745017
申请日：1996-11-07
申请人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
发明人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1214
摘要： A method for producing an electro-optical device comprising a first photolithographic step of forming a transparent pixel electrode, a second photolithographic of forming a gate electrode and a gate wiring, a third photolithographic step of forming a contact holes in an insulator film leading to the pixel electrode and the gate wiring, a fourth photolithographic step of forming a source electrode and a drain electrode and a channel portion above the gate electrode, and a fifth photolithographic step of forming a contact hole in a passivation film and isolating the semi-conductor active film below the source electrode, the drain electrode and the source wiring from other adjacent portions.The number of photolithographic steps can be reduced, to improve the yield and decrease the production cost adjacent thin film transistors.
摘要翻译： 一种用于制造电光装置的方法，包括形成透明像素电极的第一光刻步骤，形成栅电极的第二光刻和栅极布线;第三光刻步骤，在导致所述绝缘膜的绝缘膜中形成接触孔 像素电极和栅极布线;在栅电极上形成源电极和漏电极以及沟道部分的第四光刻步骤，以及在钝化膜中形成接触孔并隔离半导体活性物质的第五光刻步骤 薄膜下面的源电极，漏电极和源极布线与其他相邻部分。 可以减少光刻步骤的数量，以提高相邻薄膜晶体管的产量并降低生产成本。
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公开(公告)号：US5755938A
公开(公告)日：1998-05-26
申请号：US556188
申请日：1995-11-09
申请人： Hirofumi Fukui , Masanori Miyazaki , Masami Aihara , Chisato Iwasaki , Koichi Fukuda , Yasuhiko Kasama
发明人： Hirofumi Fukui , Masanori Miyazaki , Masami Aihara , Chisato Iwasaki , Koichi Fukuda , Yasuhiko Kasama
IPC分类号： H01L21/205 , C23C14/34 , C23C16/02 , C23C16/44 , C23C16/509 , H01L21/203 , H01L21/31 , H01L21/336 , H01L21/77 , H01L31/20 , C23C16/00
CPC分类号： H01L29/66765 , C23C14/34 , C23C16/0245 , C23C16/4405 , C23C16/5096 , H01J37/34 , H01L31/202 , H01J2237/32 , H01L27/1214 , Y02E10/50 , Y02P70/521
摘要： An apparatus which allows a first film to be formed on a substrate by chemical vapor deposition (CVD) and a second film to be formed on the substrate by sputtering, wherein the processes are performed sequentially in the same deposition chamber without exposing the substrate to an oxidative atmosphere. The deposition chamber includes a first electrode and a second electrode located under the first electrode. A transfer mechanism loads a dummy target onto the first electrode and the substrate onto the second electrode prior to a CVD process. The dummy target is resistant to sputtering and thus does not contaminate the film deposited on the substrate during CVD. After CVD and prior to sputtering, the transfer mechanism unloads the dummy target and replaces it with a sputtering target for film formation by sputtering. Both the dummy target and sputtering target can be loaded and unloaded from a single pressurized storage chamber. Thus, film formation by both sputtering and CVD can be accomplished by using a single deposition chamber without removing the substrate between processes.
摘要翻译： 一种允许通过化学气相沉积（CVD）在衬底上形成第一膜和通过溅射形成在衬底上的第二膜的装置，其中在相同的沉积室中顺序地进行处理，而不将衬底暴露于 氧化气氛。 沉积室包括位于第一电极下方的第一电极和第二电极。 转移机构在CVD工艺之前将虚拟靶加载到第二电极上的第一电极和衬底上。 虚拟靶对溅射是耐受的，因此在CVD期间不会污染沉积在衬底上的膜。 在CVD之后并且在溅射之前，转移机构卸载虚拟靶并用用溅射的成膜溅射靶代替它。 虚拟靶和溅射靶都可以从单个加压储存室装载和卸载。 因此，通过溅射和CVD的成膜可以通过使用单个沉积室而不在工艺之间移除基板来实现。
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公开(公告)号：US5714407A
公开(公告)日：1998-02-03
申请号：US414973
申请日：1995-03-31
申请人： Matagoro Maeno , Masayuki Miyashita , Hirohisa Kikuyama , Tatsuhiro Yabune , Jun Takano , Hirofumi Fukui , Satoshi Miyazawa , Chisato Iwasaki , Tadahiro Ohmi , Yasuhiko Kasama , Hitoshi Seki
发明人： Matagoro Maeno , Masayuki Miyashita , Hirohisa Kikuyama , Tatsuhiro Yabune , Jun Takano , Hirofumi Fukui , Satoshi Miyazawa , Chisato Iwasaki , Tadahiro Ohmi , Yasuhiko Kasama , Hitoshi Seki
IPC分类号： C09K13/08 , H01L21/3213 , H01L21/00 , C09K13/00
CPC分类号： H01L21/32134 , C09K13/08
摘要： An etching agent and an electronic device manufacturing method using the etching agent. The etching agent contains, in a solution, hydrofluoric acid at a concentration of 0.05 to 0.5 mol/l, and halooxoacid ions, represented by the formula (XO.sub.n).sup.p- (wherein X is a halogen element, n is 3, 4 or 6, p is 1, 2 or 3), at a concentration of at least 0.01 mol/l. An electronic device manufactured using the etching agent requires only a single etching step to etch both conductive layers (such as aluminum) as well as ohmic contact layers (a-Si).
摘要翻译： 蚀刻剂和使用该蚀刻剂的电子器件制造方法。 蚀刻剂在溶液中含有浓度为0.05〜0.5mol / l的氢氟酸和由式（XOn）p-（其中X为卤素元素，n为3,4或6）表示的卤代酸离子 ，p为1,2或3），浓度为至少0.01mol / l。 使用蚀刻剂制造的电子器件仅需要蚀刻两个导电层（例如铝）以及欧姆接触层（a-Si）的单一蚀刻步骤。
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6.发明授权Method for manufacturing a thin-film transistor array and a thin-film transistor array manufactured by the method 失效通过该方法制造的薄膜晶体管阵列和薄膜晶体管阵列的制造方法
公开(公告)号：US4853755A
公开(公告)日：1989-08-01
申请号：US170996
申请日：1988-03-17
IPC分类号： G02F1/13 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/30 , H01L27/01 , H01L27/12
CPC分类号： G02F1/1368 , H01L27/016 , G02F1/136259 , G02F2001/136263 , G02F2001/13629 , Y10S438/94
摘要： In a thin-film transistor array, a plurality of gate buses and a plurality of source buses are formed on a substrate in such a manner that said gate buses are intersected with said source buses at crossover portions, and a plurality of thin-film transistors are formed on the substrate adjacent to the crossover portion, which are connected to the gate buses and source buses for a driving purpose.Furthermore, an auxiliary bus is formed on either the gate buses, or source buses, shortcircuited portions of which are cut out by means of laser trimming so as to conduct the gate buses or source buses.
摘要翻译： 在薄膜晶体管阵列中，在基板上形成多个栅极总线和多个源极总线，使得栅极总线与交叉部分处的所述源极总线相交，并且多个薄膜晶体管 形成在与交叉部分相邻的基板上，驱动目的是连接到栅极总线和源极总线。 此外，辅助总线形成在栅极总线或源极总线上，其中短路部分通过激光微调被切出，以便导通栅极总线或源极总线。
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公开(公告)号：US06518108B2
公开(公告)日：2003-02-11
申请号：US09899869
申请日：2001-07-05
申请人： Hirofumi Fukui , Chisato Iwasaki
发明人： Hirofumi Fukui , Chisato Iwasaki
IPC分类号： H01L2100
CPC分类号： H01L29/78669 , H01L29/78696
摘要： An electronic device which comprises a gate electrode on one surface of a substrate and a gate insulating film covering the substrate and the gate electrode therewith is described. The device further comprises a semiconductor active layer formed above the gate electrode and having a width smaller than the gate electrode, and a source electrode and a drain electrode formed on the semiconductor active layer through an ohmic contact layer wherein the space between the source electrode and the drain electrode kept away from each other is wider than the space between the spaced ohmic contact layers, and the substrate is irradiated with light from the other surface on which the gate electrode is not formed. A method for making the device is also described.
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公开(公告)号：US5837559A
公开(公告)日：1998-11-17
申请号：US745904
申请日：1996-11-07
申请人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
发明人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1214
摘要： A method for producing an electro-optical device comprising a first photolithographic step of forming a transparent pixel electrode, a second photolithographic of forming a gate electrode and a gate wiring, a third photolithographic step of forming a contact holes in an insulator film leading to the pixel electrode and the gate wiring, a fourth photolithographic step of forming a source electrode and a drain electrode and a channel portion above the gate electrode, and a fifth photolithographic step of forming a contact hole in a passivation film and isolating the semiconductor active film below the source electrode, the drain electrode and the source wiring from other adjacent portions. The number of photolithographic steps can be reduced, to improve the yield and decrease the production cost, adjacent thin film transistors.
摘要翻译： 一种用于制造电光装置的方法，包括形成透明像素电极的第一光刻步骤，形成栅电极的第二光刻和栅极布线;第三光刻步骤，在导致所述绝缘膜的绝缘膜中形成接触孔 像素电极和栅极布线;在栅电极上方形成源电极和漏电极以及沟道部分的第四光刻步骤，以及在钝化膜中形成接触孔并将半导体活性膜隔离在第五光刻步骤的第五光刻步骤 源电极，漏电极和源极布线。 可以减少光刻步骤的数量，以提高相邻薄膜晶体管的产量并降低生产成本。
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公开(公告)号：US5726077A
公开(公告)日：1998-03-10
申请号：US459925
申请日：1995-06-02
申请人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
发明人： Ken Kawahata , Akira Nakano , Hirofumi Fukui , Hiroyuki Hebiguchi , Kenji Yamamoto , Chisato Iwasaki
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1214
摘要： A method for producing an electo-optical device including only five photolithographic steps, including a first photolithographic step for forming a gate electrode and gate wiring, a second photolithographic step for forming a semiconductor portion above the gate electrode, a third photolithographic step for forming a contact hole through the first insulator film to the gate wiring, a fourth photolithographic step for forming a source electrode, a source wiring and a drain electrode and then forming a channel portion above the gate electrode exposing said semiconductor active film and forming a transparent pixel electrode, and a fifth photolithographic step for forming a light-permeable opening above the transparent pixel electrode, and a contact hole for source wiring and gate wiring connection terminals.
摘要翻译： 一种用于制造仅包括五个光刻步骤的电光器件的方法，包括用于形成栅电极和栅极布线的第一光刻步骤，用于在栅电极上形成半导体部分的第二光刻步骤，用于形成栅电极的第三光刻步骤 接触孔穿过第一绝缘膜到栅极布线，第四光刻步骤，用于形成源电极，源极布线和漏极，然后在栅电极上方形成通道，暴露所述半导体有源膜并形成透明像素电极 以及用于在透明像素电极上方形成透光性开口的第五光刻工序，以及用于源极配线和栅极配线连接端子的接触孔。
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公开(公告)号：US5550091A
公开(公告)日：1996-08-27
申请号：US437606
申请日：1995-05-09
申请人： Koichi Fukuda , Tomofumi Oba , Masanori Miyazaki , Hirofumi Fukui , Chisato Iwasaki , Yasuhiko Kasama , Tadahiro Ohmi , Masaru Kubota , Hitoshi Kitagawa , Akira Nakano , Osamu Yoshida
发明人： Koichi Fukuda , Tomofumi Oba , Masanori Miyazaki , Hirofumi Fukui , Chisato Iwasaki , Yasuhiko Kasama , Tadahiro Ohmi , Masaru Kubota , Hitoshi Kitagawa , Akira Nakano , Osamu Yoshida
IPC分类号： C23C14/06 , H01L21/02 , H01L21/28 , H01L21/31 , H01L21/318 , H01L21/331 , H01L21/336
CPC分类号： C23C14/0652 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28008 , H01L21/3185 , H01L28/40 , H01L29/66765
摘要： There is provided an electronic device like a TFT using a silicon nitride insulating film of a single layer structure having an excellent dielectric voltage, and a method of producing the electronic device with reliability. In the electronic device, a conductive wiring pattern is deposited on a surface of an electrically insulated substrate, and an insulating layer is formed to cover the wiring pattern and the substrate. The insulating layer is made of a silicon nitride insulating film. A contact angle .theta. between the wiring pattern and the substrate is equals 60.degree. or more, and a value Tn1/Tg of a thickness Tn1 of the silicon nitride insulating film and a thickness Tg of the wiring pattern equals 2 or more. A horizontal distance Tn2 between a rise start position, where the silicon nitride film rises because of a step of the wiring pattern and the top end of the wiring pattern, and Tn1 are in a relation where 0.6.ltoreq.Tn2/Tn1.
摘要翻译： 提供了一种使用具有优异的介电电压的单层结构的氮化硅绝缘膜的TFT的电子器件，以及可靠地制造该电子器件的方法。 在电子设备中，在电绝缘基板的表面上沉积导电布线图案，并且形成绝缘层以覆盖布线图案和基板。 绝缘层由氮化硅绝缘膜制成。 布线图案和基板之间的接触角θ等于60°以上，氮化硅绝缘膜的厚度Tn1的值Tn1 / Tg和布线图案的厚度Tg等于2以上。 由于布线图案的台阶和布线图案的上端而形成的氮化硅膜的上升起始位置和Tn1之间的水平距离Tn2为0.6
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