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47 条记录 (耗时 0.022 秒)

    Vectors for multiple gene expression
    3.
    发明授权
    Vectors for multiple gene expression 有权
    多基因表达载体

    公开(公告)号：US08337859B2

    公开(公告)日：2012-12-25

    申请号：US12599971

    申请日：2008-01-29

    申请人： Nathalie Silvestre ,  Doris Schmitt

    发明人： Nathalie Silvestre ,  Doris Schmitt

    IPC分类号： A61K39/12 ,  A61K39/235 ,  A61K39/285 ,  A61K48/00 ,  C12N15/37 ,  C12N15/861 ,  C12N15/863 ,  C12N15/85 ,  C12N7/01 ,  C12N5/10

    CPC分类号： A61K39/12 ,  A61K2039/53 ,  A61K2039/70 ,  C07K14/005 ,  C12N7/00 ,  C12N2710/20022 ,  C12N2710/20034 ,  C12N2710/24143 ,  C12N2840/20

    摘要： The present invention provides a vector for expressing at least a first and a second nucleic acid molecules which exhibit a percentage of homology of approximately 80% or greater than 80% over a portion of 40 or more continuous nucleotides and wherein said first nucleic acid molecule and/or said second nucleic acid molecule is modified so as to reduce said percentage of homology to less than 75%. The present invention also relates to substantially isolated nucleic acid molecules comprising a nucleotide sequence as defined in any of SEQ ID NO: 9-15 and 66-69. It also provides a host cell and a pharmaceutical composition comprising such a nucleic acid molecule or vector as well as their use for therapeutic or preventive purposes.

    摘要翻译： 本发明提供了用于表达至少第一和第二核酸分子的载体，其在40个或更多个连续核苷酸的一部分上表现出大约80％或大于80％的同源性百分比，其中所述第一核酸分子和 /或所述第二核酸分子被修饰以便将所述同源性百分比降低到小于75％。 本发明还涉及包含SEQ ID NO：9-15和66-69中任一项所定义的核苷酸序列的基本上分离的核酸分子。 它还提供宿主细胞和包含这种核酸分子或载体的药物组合物以及它们用于治疗或预防目的的用途。

    Bidirectional driver circuit for PCI bus systems
    6.
    发明授权
    Bidirectional driver circuit for PCI bus systems 失效
    PCI总线系统的双向驱动电路

    公开(公告)号：US5798657A

    公开(公告)日：1998-08-25

    申请号：US722485

    申请日：1996-09-27

    申请人： Gerhard Nebel ,  Vincent Frechet ,  Doris Schmitt-Landsiedel

    发明人： Gerhard Nebel ,  Vincent Frechet ,  Doris Schmitt-Landsiedel

    IPC分类号： G06F13/40 ,  H03K17/082 ,  H03K17/10 ,  H03K19/003 ,  H03K19/094

    CPC分类号： G06F13/4072 ,  H03K17/0822 ,  H03K17/102 ,  H03K19/00315 ,  H03K19/09429

    摘要： The bidirectional driver circuit for PCI bus system involves minimal circuit outlay. It is manufactured in a 3.3 technology and is essentially also operated only with 3.3 V, but is suited for a 5 V signal environment. The driver circuit has at least one selection logic (AL), a control circuit (A), a p-channel MOS transistor (M113), a first, second and third n-channel MOS transistor (M110, M111, M112). The advantage of the driver circuit is in its minimal circuit outlay.

    摘要翻译： 用于PCI总线系统的双向驱动电路涉及最小的电路开销。 它采用3.3技术制造，基本上也仅使用3.3 V，但适用于5 V信号环境。 驱动电路具有至少一个选择逻辑（AL），控制电路（A），p沟道MOS晶体管（M113），第一，第二和第三n沟道MOS晶体管（M110，M111，M112）。 驱动电路的优点在于其最小的电路开销。

    Integrated polysilicon diode contact for gain memory cells
    8.
    发明授权
    Integrated polysilicon diode contact for gain memory cells 失效
    用于增益存储单元的集成多晶硅二极管触点

    公开(公告)号：US5710448A

    公开(公告)日：1998-01-20

    申请号：US549885

    申请日：1995-10-27

    申请人： Wolfgang H. Krautschneider ,  Doris Schmitt-Landsiedel ,  Werner Klingenstein

    发明人： Wolfgang H. Krautschneider ,  Doris Schmitt-Landsiedel ,  Werner Klingenstein

    IPC分类号： H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/108

    摘要： An integrated polysilicon diode contact having multiple doped layers. A first highly doped layer of a first dopant type is deposited on a silicon substrate. A second highly doped layer of a second, different dopant type is deposited on the substrate, separated by a spacer from the first highly doped layer. A third lower doped layer of the second dopant type is deposited on the first highly doped layer and second highly doped layers, the third lower doped layer forming a p-n junction with a source region having a dopant of the first type.

    摘要翻译： 具有多个掺杂层的集成多晶硅二极管接触。 第一掺杂剂类型的第一高掺杂层沉积在硅衬底上。 第二不同掺杂剂类型的第二高度掺杂层沉积在衬底上，由第一高掺杂层的间隔物隔开。 第二掺杂剂类型的第三低掺杂层沉积在第一高掺杂层和第二高掺杂层上，第三低掺杂层与具有第一类掺杂剂的源区形成p-n结。

    Static memory having pipeline registers
    9.
    发明授权
    Static memory having pipeline registers 失效
    具有管道寄存器的静态记忆

    公开(公告)号：US5093809A

    公开(公告)日：1992-03-03

    申请号：US487932

    申请日：1990-03-05

    申请人： Doris Schmitt-Landsiedel ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Maria Wurm

    发明人： Doris Schmitt-Landsiedel ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Maria Wurm

    IPC分类号： G11C11/413 ,  G11C5/02 ,  G11C11/41 ,  G11C11/419

    CPC分类号： G11C5/025 ,  G11C11/41 ,  G11C11/419

    摘要： Static memory having pipeline registers. The static memory has a plurality of hierarchy levels connected by pipeline registers. This architecture is very beneficial since the area requirements for the drive and read-out circuits in the first hierarchy level are especially critical. Advantageously, memory cells are used which have write and read word lines as well as separate write and read data lines and which also supply a strong cell signal so that only a few components are needed for the read circuit. A new clock format with an arrangement of pipeline registers is proposed for the appertaining memory for which power consumption is reduced by disconnecting the clocks in the lower hierarchy levels, resulting in increased area savings.

    摘要翻译： 具有流水线寄存器的静态存储器。 静态存储器具有通过流水线寄存器连接的多个层级。 这种架构是非常有益的，因为第一层次驱动器和读出电路的面积要求尤其重要。 有利地，使用具有写入和读取字线以及单独的写入和读取数据线并且还提供强电池信号以使得读取电路仅需要少量组件的存储器单元。 提出了一种具有流水线寄存器布置的新时钟格式，用于通过断开较低层次级别的时钟来降低功耗的存储器，从而增加了面积节省。