-
1.发明授权
公开(公告)号：US4844989A
公开(公告)日：1989-07-04
申请号：US27928
申请日：1987-03-19
Applicant: James M. Murduck , Yves J. Lepetre , Ivan K. Schuller , John B. Ketterson
Inventor： James M. Murduck , Yves J. Lepetre , Ivan K. Schuller , John B. Ketterson
CPC classification number: H01L39/125 , H01L39/223
Abstract: A superconducting structure is formed by depositing alternate layers of aluminum nitride and niobium nitride on a substrate. Deposition methods include dc magnetron reactive sputtering, rf magnetron reactive sputtering, thin-film diffusion, chemical vapor deposition, and ion-beam deposition. Structures have been built with layers of niobium nitride and aluminum nitride having thicknesses in a range of 20 to 350 Angstroms. Best results have been achieved with films of niobium nitride deposited to a thickness of approximately 70 Angstroms and aluminum nitride deposited to a thickness of approximately 20 Angstroms. Such films of niobium nitride separated by a single layer of aluminum nitride are useful in forming Josephson junctions. Structures of 30 or more alternating layers of niobium nitride and aluminum nitride are useful when deposited on fixed substrates or flexible strips to form bulk superconductors for carrying electric current. They are also adaptable as voltage-controlled microwave energy sources.
Abstract translation: 通过在衬底上沉积氮化铝和氮化铌的交替层来形成超导结构。 沉积方法包括直流磁控管反应溅射，磁控管反应溅射，薄膜扩散，化学气相沉积和离子束沉积。 已经构建了具有20至350埃厚度的氮化铌和氮化铝层的结构。 已经将沉积厚度约为70埃的氮化铌薄膜和沉积厚度约为20埃的氮化铝实现了最佳结果。 由氮化铝单层分离的这种氮化铌膜可用于形成约瑟夫逊结。 当沉积在固定的基板或柔性条上以形成承载电流的体超导体时，氮化铌和氮化铝的30个或更多个交替层的结构是有用的。 它们也适用于电压控制的微波能量源。
-
2.发明授权公开(公告)号：US06335108B1
公开(公告)日：2002-01-01
申请号：US09657203
申请日：2000-09-07
Applicant: John R. LaGraff , Claire L. Pettiette-Hall , James M. Murduck , Hugo W-K. Chan
Inventor： John R. LaGraff , Claire L. Pettiette-Hall , James M. Murduck , Hugo W-K. Chan
IPC: H01L3924
CPC classification number: H01L39/2464 , H01L39/249 , Y10S428/93 , Y10S505/73
Abstract: An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial template's crystalline structure.
Abstract translation: 提供了一种植入物图案超导装置和用于氧化物超导材料的间接注入图案化的方法。 该方法形成在衬底上具有氧化物超导层的器件，在氧化物超导层顶部沉积钝化层，并通过钝化层在超导层的选定部分中埋入化学杂质。 这改变了氧化物超导层的选定部分的电导率，并且将所选择的部分与氧化物超导层的未选择部分电隔离。 钝化层由比氧化物超导层更不易受植入物损伤的材料制成，以允许抑制氧化物超导层，同时保护氧化物超导层的顶表面的晶体结构并保持其平坦化。 钝化层优选是具有与氧化物超导层的晶格结构相容的晶格结构的电介质材料。 该方法对于具有多层氧化物超导材料的器件的制造特别有效，因为它不会降解外延模板的晶体结构。
-
3.发明授权
公开(公告)号：US6055723A
公开(公告)日：2000-05-02
申请号：US88207
申请日：1998-06-01
Applicant: Gershon Akerling , James M. Murduck
Inventor： Gershon Akerling , James M. Murduck
CPC classification number: H01L24/10 , H01L23/3171 , H01L24/13 , H01L39/2474 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01006 , H01L2924/01009 , H01L2924/01022 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/19042 , H01L2924/30107 , Y10T29/49144 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: The invention relates to a method for producing an electrical connection to a high temperature superconductor (HTS) circuit, where a polymer material is applied to the HTS surface covering the circuit contact disposed on one surface of the HTS circuit, a via is created in the polymer material exposing the circuit contact, a diffusion barrier is applied into the via covering the circuit contact; and, a solder bump is applied to the diffusion barrier.
Abstract translation: 本发明涉及一种用于生产与高温超导体（HTS）电路的电连接的方法，其中将聚合物材料施加到覆盖设置在HTS电路的一个表面上的电路触点的HTS表面上，在 暴露电路接触的聚合物材料，扩散屏障被施加到覆盖电路接触件的通孔中; 并且将焊料凸块施加到扩散阻挡层。
-
Patent Agency Ranking
公开(公告)号：US5863868A
公开(公告)日：1999-01-26
申请号：US937372
申请日：1997-09-25
Applicant: Hugo Wai-Kung Chan , Kenneth P. Daly , James M. Murduck
Inventor： Hugo Wai-Kung Chan , Kenneth P. Daly , James M. Murduck
CPC classification number: H01L39/225
Abstract: A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16. A magnetic field substantially parallel to the substrate applied to the SQUID hole modulates a critical current flowing through the junctions while minimizing magnetic field penetration into the junctions and minimizing SQUID loop inductance.
Abstract translation: SQUID 10是多个连接点，每个连接点允许临界电流流过。 SQUID 10包括层状结构，包括：（a）基本平坦的基板12; （b）沉积在基板上的基本均匀厚度的第一高温超导层14; （c）沉积在第一超导层14上的电介质层16，介电层16包括平坦的电平段18，该平面电平段18具有在相对端20处限定SQUID结并限定SQUID孔的两个斜坡段; 和（d）沉积在电介质层16上的基本上均匀厚度的第二高温超导层24，第二高温超导层24覆盖电介质层16的所有三个段。基本上平行于衬底的磁场施加到 SQUID空穴调制流过结的临界电流，同时最小化磁场穿入接头并最小化SQUID回路电感。
-
5.发明授权Using ion implantation to create normal layers in superconducting-normal-superconducting Josephson junctions 失效使用离子注入在超导正常超导约瑟夫逊结中产生正常层公开(公告)号：US06188919B1
公开(公告)日：2001-02-13
申请号：US09314774
申请日：1999-05-19
Applicant: John R. LaGraff , James M. Murduck , Hugo W-K. Chan
Inventor： John R. LaGraff , James M. Murduck , Hugo W-K. Chan
IPC: H01L2906
CPC classification number: H01L39/2496 , Y10S505/702
Abstract: A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.
Abstract translation: 提供SNS约瑟夫逊结（10）用于超导集成电路。 SNS结（10）包括沉积和图案化在衬底（18）上的第一高温超导（HTS）层（14），使得第一HTS层（14）被选择性地去除以暴露衬底的顶表面 18），并且在与衬底（18）的暴露的顶表面相邻的第一HTS层（14）上形成角度侧表面（22）。 离子注入用于形成沿着第一HTS层（14）的角度侧表面（22）具有非超导特性的结区域（12）。 然后在第一HTS层（14）的至少一部分和衬底（18）的暴露的顶表面上沉积和图案化第二HTS层（16），由此形成SNS约瑟夫逊结。
-
公开(公告)号：US5286336A
公开(公告)日：1994-02-15
申请号：US952011
申请日：1992-11-02
Applicant: Hugo W. Chan , Arnold H. Silver , Robert D. Sandell , James M. Murduck
Inventor： Hugo W. Chan , Arnold H. Silver , Robert D. Sandell , James M. Murduck
CPC classification number: H01L39/223 , H01L39/2493 , Y10S505/728 , Y10S505/832
Abstract: A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.
Abstract translation: 约瑟夫逊结及其制造方法，其中在基极接触件的侧边缘上原位形成层叠接合层。 层叠结层形成本发明的约瑟夫逊结，并且包括夹在超导基极和超导对电极之间的绝缘或阻挡层。 约瑟夫逊结形成在基极电极接触件的侧边缘上，以允许使用常规光学光刻技术（例如光刻）来制造非常小的结面积。 层叠接合层是原位形成的，层叠结合层的三层依次形成，而不会从沉积系统的受控气氛中移除该装置，以防止接合区域的污染。
-
7.发明申请Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices 审中-公开制造碳纳米管和碳纳米管器件的方法和装置公开(公告)号：US20080296562A1
公开(公告)日：2008-12-04
申请号：US11806365
申请日：2007-05-31
Applicant: James M. Murduck , John Douglas Adam , James E. Baumgardner , Aaron A. Pesetski , Hong Zhang Pesetski , John Xavier Przybysz
Inventor： James M. Murduck , John Douglas Adam , James E. Baumgardner , Aaron A. Pesetski , Hong Zhang Pesetski , John Xavier Przybysz
CPC classification number: H01L51/0541 , B82Y10/00 , C25D7/12 , C25D11/26 , C25D17/001 , H01L51/0018 , H01L51/0048
Abstract: Methods and apparatus for fabricating carbon nanotubes (CNTs) and carbon nanotube devices. These include a method of fabricating self-aligned CNT field-effect transistors (FET), a method and apparatus of selectively etching metallic CNTs and a method and apparatus of fabricating an oxide in a carbon nanotube (CNT) device. These methods and apparatus overcome many of the disadvantages and limitations of the prior art.
Abstract translation: 制造碳纳米管（CNT）和碳纳米管装置的方法和装置。 这些包括制造自对准CNT场效应晶体管（FET）的方法，选择性蚀刻金属CNT的方法和装置以及在碳纳米管（CNT）器件中制造氧化物的方法和装置。 这些方法和装置克服了现有技术的许多缺点和局限性。
-
公开(公告)号：US6147032A
公开(公告)日：2000-11-14
申请号：US314772
申请日：1999-05-19
Applicant: John R. LaGraff , Claire L. Pettiette-Hall , James M. Murduck , Hugo W-K. Chan
Inventor： John R. LaGraff , Claire L. Pettiette-Hall , James M. Murduck , Hugo W-K. Chan
CPC classification number: H01L39/2464 , H01L39/249 , Y10S428/93 , Y10S505/73
Abstract: An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial template's crystalline structure.
Abstract translation: 提供了一种植入物图案超导装置和用于氧化物超导材料的间接注入图案化的方法。 该方法形成在衬底上具有氧化物超导层的器件，在氧化物超导层顶部沉积钝化层，并通过钝化层在超导层的选定部分中埋入化学杂质。 这改变了氧化物超导层的选定部分的电导率，并且将所选择的部分与氧化物超导层的未选择部分电隔离。 钝化层由比氧化物超导层更不易受植入物损伤的材料制成，以允许抑制氧化物超导层，同时保护氧化物超导层的顶表面的晶体结构并保持其平坦化。 钝化层优选是具有与氧化物超导层的晶格结构相容的晶格结构的电介质材料。 该方法对于具有多层氧化物超导材料的器件的制造特别有效，因为它不会降解外延模板的晶体结构。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.011 seconds)
