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    Fabrication of discrete thin film wiring structures
    1.
    发明授权
    Fabrication of discrete thin film wiring structures 失效
    分立薄膜布线结构的制造

    公开(公告)号：US5224265A

    公开(公告)日：1993-07-06

    申请号：US783959

    申请日：1991-10-29

    申请人： John B. Dux ,  Janet L. Poetzinger ,  Roseanne M. Prestipino ,  Kevin L. Siefering

    发明人： John B. Dux ,  Janet L. Poetzinger ,  Roseanne M. Prestipino ,  Kevin L. Siefering

    IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K1/05 ,  H05K1/09 ,  H05K3/28 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

    CPC分类号： H05K3/462 ,  H01L21/4857 ,  H01L23/5384 ,  H01L23/5385 ,  H05K3/4069 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/05 ,  H05K1/095 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/063 ,  H05K2203/066 ,  H05K3/281 ,  H05K3/429 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： Multilayer thin film structures are fabricated in a parallel manner by creating testable sub-units and then joining them together to form a finished three-dimensional wiring matrix. Thus, there is disclosed a process for the fabrication of a thin film wiring structure including the steps of:forming a core wiring structure which includes the steps of:a. providing a low expansion, metallic, patterned core material;b. encapsulating the core material in a dielectric material;c. forming vias in the dielectric material; andd. metallizing the dielectric material in the vias and on the surface of the dielectric material;forming at least one cover laminate which includes dielectric material and a low expansion, metallic carrier;laminating the at least one cover laminate to the core wiring structure wherein the dielectric material of the cover laminate is in contact with the core wiring structure;forming vias through the cover laminate, the vias communicating with the vias in the core wiring structure; and filling the vias in the cover laminate and the core wiring structure with a conductive material, thereby forming a thin film wiring sub-unit.Thereafter, a plurality of such sub-units are fabricated simultaneously, tested and then stacked and aligned on a stiffener, such as multilayer ceramic substrate, before being laminated to form a three-dimensional wiring matrix.

    摘要翻译： 通过制造可测试的子单元然后将它们连接在一起以形成完成的三维布线矩阵，以并行方式制造多层薄膜结构。 因此，公开了一种制造薄膜布线结构的方法，包括以下步骤：形成芯布线结构，其包括以下步骤：a。 提供低膨胀，金属，图案化的芯材料; b。 将芯材料包封在电介质材料中; C。 在电介质材料中形成通孔; 和d。 在介电材料的通孔和表面上金属化电介质材料; 形成包括介电材料和低膨胀金属载体的至少一个覆盖层压体; 将所述至少一个覆盖层压体层压到所述芯线路结构，其中所述覆盖层压体的电介质材料与所述芯线路结构接触; 通过所述覆盖层叠体形成通孔，所述通孔与所述芯线路结构中的通孔连通; 并且用导电材料填充覆盖层叠体和芯线路结构中的通孔，从而形成薄膜布线子单元。 此后，在层压之前，多个这样的子单元同时制造，测试，然后堆叠并对准在诸如多层陶瓷基板的加强件上，以形成三维布线矩阵。

    Discrete fabrication of multi-layer thin film, wiring structures
    2.
    发明授权
    Discrete fabrication of multi-layer thin film, wiring structures 失效
    分层制造多层薄膜，布线结构

    公开(公告)号：US5232548A

    公开(公告)日：1993-08-03

    申请号：US784345

    申请日：1991-10-29

    申请人： Scott G. Ehrenberg ,  L. Wynn Herron ,  Ekkehard F. Miersch ,  Jae Park ,  Janet L. Poetzinger

    发明人： Scott G. Ehrenberg ,  L. Wynn Herron ,  Ekkehard F. Miersch ,  Jae Park ,  Janet L. Poetzinger

    IPC分类号： H05K1/05 ,  H05K3/28 ,  H05K3/46

    CPC分类号： H05K3/462 ,  H05K1/05 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0338 ,  H05K2203/066 ,  H05K2203/1572 ,  H05K3/281 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49165 ,  Y10T428/24917

    摘要： A multilayer, three-dimensional wiring matrix is fabricated from a plurality of individually testable plane pair sub-units (30). Each of the plane pair sub-units (30) includes a compensator (20) with capping layers (32) laminated on either side. The compensator (20) has a dielectric (14) encapsulated foil (10) which has been patterned with holes (12). Metallization patterns on the surfaces of the compensator (20) provide orthogonal wiring (22), electrical connections (24) to the foil (10), and electrical connections (26) between the top and bottom surfaces. The capping layer (32) includes joining metallurgy (38) at selected locations within a dielectric layer (36) that is in registry with the metallization in the vias (16). The joining metallurgy (38) may be a metal loaded thermoplastic and provides a seal for the vias (16) as well as planarizes the structure. The capping layers (32) may be formed in-situ on the compensator or separately.

    摘要翻译： 由多个可单独测试的平面对子单元（30）制造多层三维布线矩阵。 每个平面对子单元（30）包括具有层叠在任一侧的封盖层（32）的补偿器（20）。 补偿器（20）具有已经用孔（12）构图的电介质（14）封装箔（10）。 补偿器（20）的表面上的金属化图案提供正交布线（22），到箔片（10）的电连接（24）以及顶表面和底表面之间的电连接（26）。 封盖层（32）包括在与通孔（16）中的金属化对准的电介质层（36）内的选定位置处的接合冶金（38）。 接合冶金（38）可以是金属负载的热塑性材料，并为通孔（16）提供密封以及平坦化结构。 封盖层（32）可以在补偿器上原位形成或分开形成。