Inductors and Methods for Integrated Circuits
    2.
    发明申请
    Inductors and Methods for Integrated Circuits 有权
    集成电路的电感和方法

    公开(公告)号:US20130071983A1

    公开(公告)日:2013-03-21

    申请号:US13677061

    申请日:2012-11-14

    IPC分类号: H01L49/02

    摘要: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

    摘要翻译: 用于集成电路的电感器和方法,其导致尺寸与集成电路兼容的电感器,允许制造电感器,在第一晶片上具有或不具有附加电路,以及将晶片连接到第二晶片,而不浪费晶片面积。 第一晶片中的电感器由在第一晶片的每个表面处的导体形成的线圈组成,该线圈与穿过第一晶片的孔中的导体相连接。 公开了各种实施例。

    Method and Apparatus for Controlling Paintball Loading Using a Detent
    7.
    发明申请
    Method and Apparatus for Controlling Paintball Loading Using a Detent 有权
    使用夹具控制彩弹装载的方法和装置

    公开(公告)号:US20120325192A1

    公开(公告)日:2012-12-27

    申请号:US13168632

    申请日:2011-06-24

    IPC分类号: F41B11/02 F41B11/00

    CPC分类号: F41B11/70 F41B11/50 F41B11/72

    摘要: A paintball assembly capable of retaining a paintball in a loading chamber using a paintball catcher is disclosed. The paintball assembly includes a loading chamber, a detent, and a bolt. The loading chamber is coupled to a loading port to receive paintballs. In one embodiment, the detent includes a paintball catcher capable of catching the paintball as it is loaded into the loading chamber. In one example, the paintball catcher is a flexible paintball catcher extending into the loading chamber and is able to catch the paintball and hold it in a predefined position. When a trigger is pulled, the bolt pushes the paintball into a firing chamber while the paintball catcher releases the paintball.

    摘要翻译: 公开了一种能够使用彩弹捕获器在装载室中保持彩弹的彩弹组件。 彩弹组件包括装载室,制动器和螺栓。 装载室联接到装载口以接收彩弹。 在一个实施例中,制动器包括一个能够在彩弹被装载到装载室中时捕捉彩弹的彩弹捕获器。 在一个示例中,彩弹捕获器是延伸到装载室中的灵活的彩弹捕获器,并且能够捕捉彩弹并将其保持在预定位置。 当扳机被拉动时,螺栓将彩弹球推入射击室,而彩弹捕手则释放彩弹。

    Dual feed adapter of paintball marker
    8.
    发明授权
    Dual feed adapter of paintball marker 有权
    彩弹标枪双进给适配器

    公开(公告)号:US07921836B2

    公开(公告)日:2011-04-12

    申请号:US12436806

    申请日:2009-05-07

    申请人: Khanh Tran

    发明人: Khanh Tran

    IPC分类号: F41B11/00

    CPC分类号: F41B11/55 F41A9/38 F41B11/52

    摘要: A paintball marker includes a main body and a dual feed adapter coupled to the main body. The dual feed adapter has a hollow interior, a top feed port and a bottom feed port. A top feed storage hopper is detachably connected to the dual feed adapter at the top feed port, and a bottom feed storage magazine is detachably connected to the dual feed adapter at the bottom feed port. A sleeve with an opening is rotatable within the dual feed adapter between a first position where the sleeve opening aligns with the top feed port for feeding therethrough a first group of paintballs from the hopper, and a second position where the sleeve opening aligns with the bottom feed port for feeding therethrough a second group of paintballs from the magazine.

    摘要翻译: 彩弹标记器包括主体和耦合到主体的双馈进给适配器。 双进给适配器具有中空内部,顶部进料口和底部进料口。 顶部进料储存料斗在顶部进料口处可拆卸地连接到双进料适配器,并且底部进料存储盒可拆卸地连接到底部进料口处的双进料适配器。 具有开口的套筒可在双进给适配器内在第一位置和第二位置之间旋转,第一位置和第二位置之间,其中套筒开口与顶部进料口对准,用于从料斗通过第一组彩弹,以及第二位置,其中套筒开口与底部 馈送端口,用于从盒中馈送第二组彩弹。

    Globally planarized backend compatible thin film resistor contact/interconnect process
    9.
    发明授权
    Globally planarized backend compatible thin film resistor contact/interconnect process 有权
    全局平面化后端兼容薄膜电阻接触/互连过程

    公开(公告)号:US06607962B2

    公开(公告)日:2003-08-19

    申请号:US09925945

    申请日:2001-08-09

    IPC分类号: H01L2120

    摘要: A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.

    摘要翻译: 形成薄膜电阻器触点的方法包括蚀刻停止材料,以保护下面的薄膜电阻器免受后来的干蚀刻工艺以形成对薄膜电阻器的接触开口。 更具体地,该方法包括形成薄膜电阻器,在薄膜电阻器上形成第一电介质层,形成穿过第一电介质层的第一开口以暴露薄膜电阻器的下面部分,在该薄膜电阻器的内部形成蚀刻停止 第一介电层的第一开口,在蚀刻停止层和第一介电层上方形成第二介电层,形成通过第二介电层的第二开口以暴露蚀刻停止层的下面部分,并在其内形成金属塞 第二接触开口,其中金属插塞通过蚀刻停止与薄膜电阻器电接触。 或者,在绝缘蚀刻停止的情况下,穿过介电层的第二开口通过蚀刻停止,并且在第二接触开口内形成金属插塞,其中金属插塞与薄膜直接电接触 电阻。

    Low-K sub spacer pocket formation for gate capacitance reduction
    10.
    发明授权
    Low-K sub spacer pocket formation for gate capacitance reduction 有权
    用于栅极电容降低的低K子间隔袋形成

    公开(公告)号:US06351013B1

    公开(公告)日:2002-02-26

    申请号:US09352339

    申请日:1999-07-13

    IPC分类号: H01L31062

    摘要: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

    摘要翻译: 通过在源极/漏极区域之上的栅电极的角部形成低介电常数(K)材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后,在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区,从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时,在栅极电极和源极/漏极区域之间表现出减小的电容。