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    Method for controlling warpage in redistributed chip packaging panels
    1.
    发明授权
    Method for controlling warpage in redistributed chip packaging panels 有权
    控制再分配芯片封装板翘曲的方法

    公开(公告)号：US07950144B2

    公开(公告)日：2011-05-31

    申请号：US12112489

    申请日：2008-04-30

    申请人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

    发明人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

    IPC分类号： H05K3/30

    CPC分类号： H01L21/67288 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/96 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49171 ,  H01L2924/00

    摘要： A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

    摘要翻译： 公开了一种用于控制集成电子面板组件中的翘曲的方法，其包括嵌入密封剂内的多个管芯。 该方法包括确定集成面板组件所需的累积层数。 每个积层对于集成电子面板组件贡献一定量的凹陷。 然后预测集成面板组件上的全局凸起翘曲的水平，其中全局凸起翘曲由嵌入式接地平面（EGP）单独存在于集成面板组件内并且在没有任何积聚层的情况下提供。 嵌入式接地平面包括用于在相应的开口内接受至少一个模具的开口，并且其有助于固定量的全局凸起翘曲。 然后确定要引入集成电子面板组件的局部凸起翘曲的量，其与固定量的全局凸起翘曲一起提供到集成电子面板组件的组合凸起翘曲。 因此，全局和局部凸起翘曲抵消随后通过积层处理引入的凹面，并且足以使得完整的集成电子面板组件能够进行后续的平面处理。

    METHOD FOR CONTROLLING WARPAGE IN REDISTRIBUTED CHIP PACKAGING PANELS
    2.
    发明申请
    METHOD FOR CONTROLLING WARPAGE IN REDISTRIBUTED CHIP PACKAGING PANELS 有权
    用于控制重新排列的芯片包装面板中的WARPAGE的方法

    公开(公告)号：US20090271980A1

    公开(公告)日：2009-11-05

    申请号：US12112489

    申请日：2008-04-30

    申请人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

    发明人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

    IPC分类号： H05K7/02

    CPC分类号： H01L21/67288 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/96 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49171 ,  H01L2924/00

    摘要： A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

    摘要翻译： 公开了一种用于控制集成电子面板组件中的翘曲的方法，其包括嵌入密封剂内的多个管芯。 该方法包括确定集成面板组件所需的累积层数。 每个积层对于集成电子面板组件贡献一定量的凹陷。 然后预测集成面板组件上的全局凸起翘曲的水平，其中全局凸起翘曲由嵌入式接地平面（EGP）单独存在于集成面板组件内并且在没有任何积聚层的情况下提供。 嵌入式接地平面包括用于在相应的开口内接受至少一个模具的开口，并且其有助于固定量的全局凸起翘曲。 然后确定要引入集成电子面板组件的局部凸起翘曲的量，其与固定量的全局凸起翘曲一起提供到集成电子面板组件的组合凸起翘曲。 因此，全局和局部凸起翘曲抵消随后通过积层处理引入的凹面，并且足以使得完整的集成电子面板组件能够进行后续的平面处理。

    Method of forming a packaged semiconductor device
    3.
    发明授权
    Method of forming a packaged semiconductor device 有权
    形成封装半导体器件的方法

    公开(公告)号：US08216918B2

    公开(公告)日：2012-07-10

    申请号：US12842562

    申请日：2010-07-23

    申请人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

    发明人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

    IPC分类号： H01L21/00 ,  H01L21/322

    CPC分类号： H01L21/6835 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2203/1469

    摘要： A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

    摘要翻译： 使用一种方法来形成封装的半导体器件。 具有活性表面的半导体器件被放置在电路板的开口中。 电路板具有第一主表面和具有开口的第二主表面，在第一主表面和第二主表面之间延伸的第一通孔，第一接触垫在第一主表面处终止通孔，第二接触垫终止 第二个主要表面的通孔。 电介质层被施加在半导体器件和电路板的第二主表面上。 在电介质层上形成互连层。 互连层具有电连接到第二接触焊盘的第二通孔，电连接到半导体器件的有源表面的第三通孔，暴露表面和暴露表面处的第三接触焊盘。

    METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE 有权
    形成包装半导体器件的方法

    公开(公告)号：US20120021565A1

    公开(公告)日：2012-01-26

    申请号：US12842562

    申请日：2010-07-23

    申请人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

    发明人： Zhiwei Gong ,  Scott M. Hayes ,  George R. Leal ,  Douglas G. Mitchell ,  Jason R. Wright ,  Jianwen Xu

    IPC分类号： H01L21/58

    CPC分类号： H01L21/6835 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2203/1469

    摘要： A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

    摘要翻译： 使用一种方法来形成封装的半导体器件。 具有活性表面的半导体器件被放置在电路板的开口中。 电路板具有第一主表面和具有开口的第二主表面，在第一主表面和第二主表面之间延伸的第一通孔，第一接触垫在第一主表面处终止通孔，第二接触垫终止 第二个主要表面的通孔。 电介质层被施加在半导体器件和电路板的第二主表面上。 在电介质层上形成互连层。 互连层具有电连接到第二接触焊盘的第二通孔，电连接到半导体器件的有源表面的第三通孔，暴露表面和暴露表面处的第三接触焊盘。

    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
    5.
    发明申请
    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE 有权
    用于在半导体器件上镀膜特征的熔断母线

    公开(公告)号：US20130023091A1

    公开(公告)日：2013-01-24

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Fused buss for plating features on a semiconductor die
    6.
    发明授权
    Fused buss for plating features on a semiconductor die 有权
    熔融母线用于半导体管芯上的电镀特征

    公开(公告)号：US08349666B1

    公开(公告)日：2013-01-08

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82 ,  H01L21/332 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Fine pitch interconnect and method of making
    10.
    发明授权
    Fine pitch interconnect and method of making 有权
    细间距互连及制作方法

    公开(公告)号：US07528069B2

    公开(公告)日：2009-05-05

    申请号：US11267975

    申请日：2005-11-07

    申请人： Robert J. Wenzel ,  George R. Leal

    发明人： Robert J. Wenzel ,  George R. Leal

    IPC分类号： H01L21/44

    CPC分类号： H01L23/485 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

    摘要： Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent contact pads are present in the same opening in the dielectric. The traces to the contact pads are in a line so that no widening is required where the lines make contact to the contact pads. The lines can be widened before they get to the contact pads but at the contact pads, they are substantially at the minimum width for the line. Thus, the contact pads can be at a pitch much lower than if capture pads were used.

    摘要翻译： 通过使用延伸到触点的迹线而不需要接触焊盘上的捕获垫来实现细间距触点。 最好避免捕获垫，因为它们的直径大于它们所连接的线的直径。 优选地，相邻的接触垫存在于电介质中的相同的开口中。 接触焊盘的迹线处于一条直线上，因此在线路接触到接触焊盘时不需要加宽。 线可以在它们到达接触垫之前被加宽，但是在接触垫处，它们基本上处于线的最小宽度。 因此，接触焊盘的间距可以比使用捕获焊盘要低得多。